AD6636BBCZ1 datasheet(39/72 Pages) AD

39 / 72 page

AD6636

Rev. 0 | Page 39 of 72

Biphase Filtering Option

The second special function that can be performed by the

second subblock of the output data router is called the biphase

filtering option. With this option, the AD6636 can be used to

process data from ADCs that run faster than the input clock

frequency by using two channels or two streams to form a

biphase filter.

For example, a 300 MHz ADC can be used with a clock rate of

150 MHz driving the ADC. The ADC data can be decimated by

2 to produce even and odd data streams of data. The even

stream can be clocked into ADC Input Port A, and the odd

stream can be clocked into ADC Input Port B. These input ports

drive separate channels or separate groups of channels. The

filters of the RCF can be designed to place a 300 MHz sample

time difference (1/300 MHz = 3.3 ns) between the even and odd

path filters.

After the channel-filter coefficients have appropriate delay, a

complex addition of the odd and even sample channels can be

performed to create a single filter. This equivalent filter looks

like a single channel with a 300 MHz input rate, even though

the clock rate of the chip runs at only 150 MHz.

A biphase filter summation is implemented by the following

equation:

Output = (Ie × Ce + Io × Co) + j(Qe × Ce + Qo × Co)

where:

Ie × Ce, Qe × Ce are even in-phase and quadrature-phase

samples from one stream.

Io × Co and Qo × Co are odd in-phase and quadrature-phase

samples from the other stream.

Ce and Co are the even and odd coefficients, which differ by

1 high speed sample time (300 MHz in the previous example).

Users can program certain streams to be summed using the

biphase filtering option. This option can be programmed using

the same 3-bit complex control word in the Parallel Output

Control 2 register. The values for the 3-bit control word and

their corresponding settings are listed in Table 23.

AUTOMATIC GAIN CONTROL

The AD6636 is equipped with six independent automatic gain

control (AGC) loops that directly follow the second data router

and immediately precede the parallel output ports. Each AGC

circuit has 96 dB of range. It is important that the decimating

filters of the AD6636 preceding the AGC reject unwanted

signals, so that each AGC loop is operating only on the carrier

of interest, and carriers at other frequencies do not affect the

ranging of the loop.

The AGC compresses the 24-bit complex output from the

second data router into a programmable word size of 4 to 8, 10,

12, or 16 bits. Because the small signals from the lower bits are

pushed in to higher bits by adding gain, the clipping of the

lower bits does not compromise the SNR of the signal of

interest.

The AGC maintains a constant mean power on the output

despite the level of the signal of interest, allowing operation in

environments where the dynamic range of the signal exceeds

the dynamic range of the output resolution. The output width of

the AGC is set by writing a 3-bit AGC word length word in the

AGC control register of the individual channel’s memory map.

The AGC can be bypassed, if needed, and, when bypassed, the

24-bit complex input word is still truncated to a 16-bit value

that is output through the parallel port output. The six AGCs

available on the AD6636 are programmable through the six

channel memory maps. AGCs corresponding to individual

channels can be bypassed by writing Logic 1 to AGC bypass bit

in the AGC control register.

Three sources of error can be introduced by the AGC function:

underflow, overflow, and modulation. Underflow is caused by

truncation of bits below the output range. Overflow is caused by

clipping errors when the output signal exceeds the output range.

Modulation error occurs when the output gain varies while

receiving data.

The desired signal level should be set based on the probability

density function of the signal, so that the errors due to under-

flow and overflow are balanced. The gain and damping values

of the loop filter should be set, so that the AGC is fast enough to

track long-term amplitude variations of the signal that might

cause excessive underflow or overflow, but slow enough to avoid

excessive loss of amplitude information due to the modulation

of the signal.

AGC Loop

The AGC loop is implemented using a log-linear architecture. It

contains four basic operations: power calculation, error calcula-

tion, loop filtering, and gain multiplication.

The AGC can be configured to operate in either desired signal

level mode or desired clipping level mode. The mode is set by

the AGC clipping error bit of the AGC control register. The

AGC adjusts the gain of the incoming data according to how far

it is from a given desired signal level or desired clipping level,

depending on the selected mode of operation.

Two datapaths to the AGC loop are provided: one before the

clipping circuitry and one after the clipping circuitry, as shown

in Figure 39. For the desired signal level mode, only the I/Q

path from before the clipping is used. For the desired clipping

level mode, the difference of the I/Q signals from before and

after the clipping circuitry is used.

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