AD6636BBCZ1 datasheet(19/72 Pages) AD

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AD6636

Rev. 0 | Page 19 of 72

THEORY OF OPERATION

ADC INPUT PORT

The AD6636 features four identical, independent high speed

ADC input ports named A, B, C, and D. These input ports have

the flexibility to allow independent inputs, diversity inputs, or

complex I/Q inputs. Any of the ADC input ports can be routed

to any of the six tuner channels; that is, any of the six AD6636

channels can receive input data from any of the input ports.

Time-multiplexed inputs on a single port are not supported in

the AD6636.

These four input ports can operate at up to 150 MSPS. Each

input port has its own clock (CLKA, CLKB, CLKC, and CLKD)

used for registering input data into the AD6636. To allow slow

input rates while providing fast processing clock rates, the

AD6636 contains an internal PLL clock multiplier that supplies

the internal signal processing clock. CLKA is used as an input to

the PLL clock multiplier. Additional programmability allows the

input data to be clocked into the part either on the rising edge

or the falling edge of the input clock.

In addition, the front end of the AD6636 contains circuitry that

enables high speed signal-level detection, gain control, and

quadrature I/Q correction. This is accomplished with a unique

high speed level-detection circuit that offers minimal latency

and maximum flexibility to control all four input signals

(typically ADC inputs) individually. The input ports also

provide input power-monitoring functions via various modes,

and magnitude and phase I/Q correction blocks. See the

Quadrature I/Q Correction Block section for details.

Each individual processing channel can receive input data from

any of the four input ports individually. This is controlled using

3-bit crossbar mux-select bit words in ADC input control

addition to the four input ports, an internal test signal (PN—

pseudorandom noise sequence) can also be selected. This

internal test signal is discussed in the User-Configurable Built-

In Self-Test (BIST) section.

Input Data Format

Each input port consists of a 16-bit mantissa and a 3-bit

exponent (16 + 3 floating-point input, or up to 16-bit fixed-

point input). When interfacing to standard fixed-point ADCs,

the exponent bit should either be connected to ground or be

programmed as outputs for gain control output. If connected to

a floating-point ADC (also called gain ranging ADC), the

exponent bits from the ADC can be connected to the input

exponent bits of the AD6636. The mantissa data format is twos

complement, and the exponent is unsigned binary.

The 3-exponent bits are shared with the gain range control bits

in the hardware. When floating-point ADCs are not used, these

three pins on each ADC input port can be used as gain range

control output bits.

Input Timing

The data from each high speed input port is latched either on

the rising edge or the falling edge of the port’s individual CLKx

(where x stands for A, B, C, or D input ports). The ADC clock

invert bit in ADC clock control register selects the edge of the

clock (rising or falling) used to register input data into the

AD6636.

INx [15:0]

EXPx [2:0]

CLKx

DATA n

DATA n + 1

tSI

tHI

Figure 21. Input Data Timing Requirements

(Rising Edge of Clock, x = A, B, C, or D for Four Input Ports)

INx [15:0]

EXPx [2:0]

CLKx

DATA n

DATA n + 1

tSI

tHI

Figure 22. Input Data Timing Requirements

(Falling Edge of Clock, x = A, B, C, or D for Four Input Ports)

The clock signals (CLKA, CLKB, CLKC, and CLKD) can

operate at up to 150 MHz. In applications using high speed

ADCs, the ADC sample clock, data valid, or data ready strobe

are typically used to clock the AD6636.

Connection to Fixed-Point ADC

For fixed-point ADCs, the AD6636 exponent inputs, EXP[2:0],

are not typically used and should be tied low. Alternatively,

because these pins are shared with gain range control bits, if the

gain ranging block is used, these pins can be used as outputs of

the gain range control block. The ADC outputs are tied directly

to the AD6636 inputs, MSB-justified. Therefore, for fixed-point

ADCs, the exponents are typically static and no input scaling is

used in the AD6636. Figure 23 shows a typical interconnection.

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