AD6636BBCZ1 datasheet(37/72 Pages) AD

37 / 72 page

AD6636

Rev. 0 | Page 37 of 72

The image rejection of this filter is about 55 dB, but is still

sufficient, because the image is from the desired signal, not an

interfering signal. Note that the interpolating half-band filter

can be enabled by writing a Logic 1 to Bit 9 of the MRCF

control registers.

The frequency response of the interpolating half-band FIR is

shown in Figure 37 with respect to the chip rate. The input rate

to this filter is 2× the chip rate, and the output rate is 4× the

chip rate.

FREQUENCY AS FRACTION OF INPUT RATE

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

–20

–40

–60

–80

–100

–53

0.75

1.25

INTERPOLATING

HALFB AND

FILTER RESPONSE

Figure 37. Interpolating Half-Band Frequency Response

OUTPUT DATA ROUTER

The output data router circuit precedes the six AGCs of the final

output block and immediately follows the interpolating half-

band filters. This block consists of two subblocks. The first

subblock is responsible for combining (interleaving) data from

more than one channel into a single stream of data.

The second subblock can perform two special functions, either

complex filter completion or biphase filtering. The combined

data is passed on to the AGCs.

Interleaving Data

In some cases, filtering using a single channel is insufficient.

For such setups, it is advantageous to combine the filtering

resources of more than one channel.

Multiple channels can be set up to work on the ADC input port

data with the same NCO and filter setups. The decimation

phase values in one of the RCF filters are set such that the

channel filters are exactly out of phase with each other. In the

data router, these multiple channels are interleaved (combined)

to form a single stream of data. Because each individual channel

is decimated more than it would be if a single channel were

filtering, a larger number of filter taps can be calculated.

For example, two channels need to work together to produce a

filter at an output rate of 10 MHz when the input rate is

100 MHz. Each channel is decimated by a factor of 20 (total

decimation) to achieve the desired output rate of 5 MHz each.

This compares to a decimation of 10, if a single channel were

filtering.

The same coefficients are programmed in both channels’ RCF

filters, and the decimation phases are set to 0 and 1. The

decimation phases can be set to 0 for one channel, and 1 for the

second channel in the pair. This causes the first channel to

produce the even outputs, and the second to produce the odd

outputs of the filter. The streams can then be recombined

(interleaved) to produce the desired 10 MHz output rate. The

benefit is that now each channel’s RCF has time to calculate

twice as many taps, because it has a lower output rate.

STREAM

CONTROL

COMPLEX

FILTER

COMPLETION

PARALLEL

PORT A

PARALLEL

PORT C

PARALLEL

PORT B

AGC0

STR0

CH0

AGC1

STR1

CH1

AGC2

STR2

CH2

AGC3

STR3

CH3

AGC4

STR4

CH4

AGC5

STR5

CH5

Figure 38. Output Data Router Block Diagram

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