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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD6636BBCZ1 датащи(PDF) 10 Page - Analog Devices |
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AD6636BBCZ1 датащи(HTML) 10 Page - Analog Devices |
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10 / 72 page  AD6636 Rev. 0 | Page 10 of 72 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 34 56 7 8 9 10 11 12 13 14 15 16 A GND INC3 IND4 IND7 CLKD CLKC IND11 GND VDDCORE IND14 IND15 SYNC1 TDO PBGAIN PB11 GND A B IND0 VDDIO INC2 IND5 IND6 IND8 IND10 IND12 IND13 INC14 SYNC3 SYNC0 TRST PBCH2 VDDIO PB12 B C EXPA1 EXPD1 INC0 INC1 IND3 INC5 IND9 INC10 INC13 SYNC2 TMS TCLK PBCH0 PB8 PB15 PB10 C D EXPB0 EXPC2 EXPC1 EXPD0 IND2 INC4 INC7 INC9 INC12 TDI PBCH1 PBIQ PB14 PB9 PB13 PACH1 D E INA14 INA15 EXPA0 LVDS_RSET GND IND1 INC6 INC8 INC11 INC15 PBREQ PBACK PB4 PB5 PB1 PCLK E F INA12 INA13 EXPB1 EXPC0 EXPD2 GND VDDIO VDDIO VDDIO VDDIO GND PB6 PB0 PB7 PAREQ PA0 F G INA11 INB13 INB15 EXPB2 EXPA2 VDDCORE GND GND GND GND VDDCORE PB3 PAGAIN PB2 PACH0 PA2 G H VDDCORE INA10 INB12 INB11 INB14 VDDCORE GND GND GND GND VDDCORE PACH2 PAIQ PAACK PA1 GND H J GND INA9 INB10 INB8 INB9 VDDCORE GND GND GND GND VDDCORE PA3 PA7 PA5 PA4 VDDCORE J K CLKA INA8 INA7 INB6 INB7 VDDCORE GND GND GND GND VDDCORE PA12 PA15 PA9 PA8 PA6 K L CLKB INA6 INB4 INB1 INB3 GND VDDIO VDDIO VDDIO VDDIO GND PC3 PCACK PCCH1 PA13 PA10 L R CPUCLK (SCLK) VDDIO MSB_ FIRST EXT_ FILTER CHIPID1 D14 D10 D11 D6 D0 A3 A1 PC9 PC6 VDDIO PCREQ R 1 2 34 56 7 8 9 10 11 12 13 14 15 16 = VDDCORE = VDDIO = GROUND M INA5 INB5 INB2 INB0 GND D13 D15 D5 A5 PC12 PC7 PC2 PC0 PCCH0 PA11 M DTACK (RDY, SDO) N INA4 INA3 INA0 CHIPID2 D12 D2 D1 A4 A0 (SDI) PC15 PC5 PC1 PCCH2 PA14 N R/W (WR, STFS) CS (SCS) P INA2 INA1 SMODE CHIPID3 GND D9 D4 A6 A2 PC11 PC10 PC4 PCIQ PCGAIN P DS (RD, SRFS) RESET T GND MODE CHIPID0 D7 D8 D3 VDDCORE GND GND A7 PC14 PC13 PC8 GND GND T IRP Figure 2. CSP_BGA Pin Configuration Table 7. Pin Names and Functions Name Type Pin No. Function POWER SUPPLY VDDCORE Power See Table 8 1.8 V Digital Core Supply. VDDIO Power See Table 8 3.3 V Digital I/O Supply. GND Ground See Table 8 Digital Core and I/O Ground. INPUT (ADC) PORTS (CMOS/LVDS) CLKA Input K1 Clock for Input Port A. Used to clock INA[15:0] and EXPA[2:0] data. Additionally, this clock is used to drive internal circuitry and PLL clock multiplier. CLKB Input L1 Clock for Input Port B. Used to clock INB[15:0] and EXPB[2:0] data. CLKC Input A6 Clock for Input Port C. Used to clock INC[15:0] and EXPC[2:0] data. CLKD Input A5 Clock for Input Port D. Used to clock IND[15:0] and EXPD[2:0] data. INA[0:15] Input See Table 8 Input Port A (Parallel). INB[0:15] Input See Table 8 Input Port B (Parallel). INC[0:15] Input See Table 8 Input Port C (Parallel). IND[0:15] Input See Table 8 Input Port D (Parallel). EXPA[0:2] Bidirectional E3, C1, G5 Exponent Bus Input Port A. Gain control output. EXPB[0:2] Bidirectional D1, F3, G4 Exponent Bus Input Port B. Gain control output. EXPC[0:2] Bidirectional F4, D3, D2 Exponent Bus Input Port C. Gain control output. EXPD[0:2] Bidirectional D4, C2, F5 Exponent Bus Input Port D. Gain control output. CLKA, CLKB Input K1, L1 LVDS Differential Clock for LVDS_A Input Port (LVDS_CLKA+, LVDS_CLKA−). |
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