AD6636BBCZ1 datasheet(20/72 Pages) AD

20 / 72 page

AD6636

Rev. 0 | Page 20 of 72

AD6645

14-BIT ADC

AD6636

D13 (MSB)

D0 (LSB)

IN15

IN2

EXP0

EXP1

IN0

IN1

EXP2

GAIN RANGING CONTROL

BITS OR GROUNDED

EXPONENT BITS

Figure 23. Typical Interconnection of the AD6645 Fixed-Point ADC

and the AD6636

Scaling with Floating-Point ADC

An example of the exponent control feature combines the

AD6600 and the AD6636. The AD6600 is an 11-bit ADC with

three bits of gain ranging. In effect, the 11-bit ADC provides the

mantissa, and the three bits of the relative signal strength

indicator (RSSI) are the exponent. Only five of the eight

available steps are used by the AD6600. See the AD6600 data

sheet for details.

Table 9. Weighting Factors for Different Exp[2:0] Values

ADC Input

Level

AD6636

Exp[2:0]

Data

Divide-By

Signal

Attenuation (dB)

Largest

000 (0)

/1 (>> 0)

001 (1)

/2 (>>1)

010 (2)

/4 (>>2)

011 (3)

/8 (>>3)

100 (4)

/16 (>> 4)

101 (5)

/32 (>> 5)

110 (6)

/64 (>> 6)

Smallest

111 (7)

/128(>> 7)

Complex (I/Q) Input Ports

The four individual ADC input ports of the AD6636 can be

configured to function as two complex input ports. Additionally,

if required, only two input ports can be made to function as a

complex port, while the remaining two input ports function as

real individual input ports.

In complex mode, Input Port A is paired with Input Port B to

receive I and Q data, respectively. Similarly, Input Port C can be

paired with Input Port D to receive I and Q data, respectively.

These two pairings are controlled individually using Bits 24 and

25 of ADC input control register.

As explained previously, each individual channel can receive

input signals from any of the four input ports using the crossbar

mux select bits in the ADC input control register. In addition to

the three bits, a 1-bit selection is provided for choosing the

complex input port option for any individual channel. For

example, if Channel 0 needs to receive complex input from

Input Ports A and B, then the mux select bits should indicate

Input Port A, and the complex input bit should be selected.

When the input ports are paired for complex input operation,

only one set of exponent bits is driven externally with gain

control output. So when Input Ports A and B form a complex

input, then EXPA[2:0] are output and, similarly, for Input Ports

C and D, EXPC[2:0] are output.

LVDS Input Ports

AD6636 input ports can be configured in two different modes:

CMOS or LVDS. In CMOS input mode, the four input ports can

be configured as two complex input ports. In LVDS mode, two

CMOS input ports each are combined to form one LVDS input

port.

CMOS Input Ports INA[15:0] and INB[15:0] form the positive

and negative differential nodes, LVDS_A+[15:0] and

LVDS_A−[15:0], respectively. Similarly, INC[15:0] and

IND[15:0] form the positive and negative differential nodes,

LVDS_C+[15:0] and LVDS_C− [15:0], respectively. CLKA and

CLKB form the differential pair, LVDS_CLKA+ and

LVDS_CLKA− pins. Similarly, CLKC and CLKD form the

differential pair LVDS_CLKC+ and LVDS_CLKC− pins.

By default, the AD6636 powers up in CMOS mode and can be

programmed to CMOS mode by using the CMOS mode bit (Bit

10 of the LVDS control register). Writing Logic 1 to Bit 8 of the

LVDS control register enables an autocalibrate routine that

calibrates the impedance of the LVDS pads to match the output

impedance of the LVDS signal source impedance. The LVDS

pads in the AD6636 have an internal impedance of 100 Ω across

the differential signals; therefore, an external resistor is not

required.

PLL CLOCK MULTIPLIER

In the AD6636, the input clock rate must be the same as the

input data rate. In a typical digital down-converter architecture,

the clock rate is a limitation on the number of filter taps that

can be calculated in the programmable RAM coefficient filters

(MRCF, DRCF, and CRCF). For slower ADC clock rates (or for

any clock rate), this limitation can be overcome by using a PLL

clock multiplier to provide a higher clock rate to the RCF filters.

Using this clock multiplier, the internal signal processing clock

rate can be increased up to 200 MHz. The CLKA signal is used

as an input to the PLL clock multiplier.

CLKA

PLL_CLK

ADC_CLK

DIVIDE BY N

(1, 2, 4 OR 8)

PLL CLOCK

MULITPLIER

(4x TO 20x)

PLL CLOCK GENERATION

BYPASS_PLL

1 FOR BYPASS

Figure 24. PLL Clock Generation

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