AD6636BBCZ1 datasheet(24/72 Pages) AD

24 / 72 page

AD6636

Rev. 0 | Page 24 of 72

Additional Control Bits

For additional flexibility in the power monitoring process, two

control bits are provided in the power-monitor control register.

The two control bits are the disable monitor period timer bit

and the clear-on-read bit. These options have the same function

in all three modes of operation.

Disable Monitor Period Timer Bit

When the disable monitor period timer bit is written with

Logic 1, the timer continues to run but does not cause the

contents of the MSR to be transferred to the holding register

when the count reaches 1. This function of transferring the

MSR to the power monitor holding register and resetting the

MSR is now controlled by a read operation on the microport or

serial port.

When a microport or serial port read is performed on the

power monitor holding register, the MSR value is transferred to

the holding register. After the read operation, the timer is

reloaded with the AMPR value. If the timer reaches 1 before the

microport or serial port read, the MSR value is not transferred

to the holding register, as in normal operation. The timer still

generates an interrupt on the AD6636 interrupt pin and updates

the interrupt status register. An interrupt appears on the IRP

pin, if interrupts are enabled in the interrupt enable register.

Clear-on-Read Bit

This control bit is valid only when the disable monitor period

timer bit is Logic 1. When both of these bits are set, a read

operation to either the microport or the serial port reads the

MSR value and the monitor period timer is reloaded with the

AMPR value. The MSR is cleared (written with current input

signal magnitude in peak power and mean power mode; written

with a zero in threshold crossing mode), and normal operation

continues.

When the monitor period timer is disabled and the clear-on-

read bit is set, a read operation to the power monitor holding

monitor loop restarts.

If the clear-on-read bit is Logic 0, the read operation to the

microport or serial port does not clear the MSR value after it is

transferred into the holding register. The value from the

previous monitor time period persists, and it continues to be

compared, accumulated, or incremented, based on new input

signal magnitude values.

QUADRATURE I/Q CORRECTION BLOCK

When the I and Q paths are digitized using separate ADCs, as in

quadrature IF down-conversion, a mismatch often occurs

between I and Q due to variations in the ADCs from the

manufacturing process. The AD6636 is equipped with two

quadrature correction blocks that can be used to correct I/Q

mismatch errors in a complex baseband input stream. These I/Q

mismatches can result in spectral distortions, and removing

them is useful.

Two such blocks are present, one each for the I/Q signal formed

by combining the A and B inputs and the C and D inputs,

respectively. The I/Q correction block can be enabled when the

Port A (or Port C) complex data active bit is enabled in the

ADC input control register. This block is bypassed when real

input data is present on the ADC input ports, because there is

no possibility of I/Q mismatch in real data.

The I/Q or quadrature correction block consists of three

independent subblocks: dc correction, phase correction, and

amplitude correction. Three individual bits in the AB (or CD)

correction control registers can be used to enable or disable

each of these subblocks independently. Figure 29 shows the

contents and definitions of the registers related to the

quadrature correction block.

ESTIMATE

MAGNITUDE

ERROR

ESTIMATION

PHASE ESTIMATE

[13:0]

PHASE

ESTIMATE

[13:0]

Q_OUT [15:0]

TO NEXT BLOCK

I_OUT [15:0]

TO NEXT BLOCK

I [15:0] FROM

INPUT PORT

Q [15:0] FROM

INPUT PORT

PHASE

ERROR

ESTIMATION

MAGNITUDE

ESTIMATE [13:0]

Figure 29. Quadrature Correction Block Diagram

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