AD6636BBCZ1 datasheet(59/72 Pages) AD

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AD6636

Rev. 0 | Page 59 of 72

<9>: Channel 5 Data Ready Enable Bit. When this bit is set, the

Channel 5 data ready interrupt is enabled, allowing an interrupt

to be generated when Channel 5 BIST signature registers are

updated. When this bit is cleared, an interrupt cannot be

generated for this event.

<8>: Channel 4 Data Ready Enable Bit. Similar to Bit <9> for

Channel 4.

<7>: Channel 3 Data Ready Enable Bit. Similar to Bit <9> for

Channel 3.

<6>: Channel 2 Data Ready Enable Bit. Similar to Bit <9> for

Channel 2.

<5>: Channel 1 Data Ready Enable Bit. Similar to Bit <9> for

Channel 1.

<4>: Channel 0 Data Ready Enable Bit. Similar to Bit <9> for

Channel 0.

<3>: ADC Port D Power Monitoring Enable Bit. When this bit is

set to Logic 1, the ADC Port D power monitoring interrupt is

enabled allowing an interrupt to be generated when ADC Port

D power monitoring registers are updated. When set to Logic 1,

the ADC Port D power monitoring interrupt is disabled.

<2>: ADC Port C Power Monitoring Enable Bit. Similar to

Bit <3> for ADC Port C.

<1>: ADC Port B Power Monitoring Enable Bit. Similar to

Bit <3> for ADC Port B.

<0>: ADC Port A Power Monitoring Enable Bit. Similar to

Bit <3> for ADC Port A.

INPUT PORT REGISTER MAP

ADC Input Control Register <27:0>

These bits are general control bits for the ADC input logic.

<27>: PN Active Bit. When this bit is set, the pseudorandom

number generator is active. When this bit is cleared, the PN

generator is disabled and the seed is set to its default value.

<26>: EXP Lock Bit. When this bit is set along with the PN

active bit, then the EXP signal for pseudorandom input is

locked to 000 (giving full-scale input). When this bit is cleared,

EXP bits for pseudorandom input are randomly generated input

data bits.

<25>: Port C Complex Data Active Bit. When this bit is set, the

data inputs on Ports C and D are interpreted as complex inputs

(Port C for the in-phase signal and Port D for the quadrature

phase signal). This complex input is passed on as the input from

ADC Port C. When this bit is cleared, the data on ADC Port C

and ADC Port D interpreted as real and independent input.

Note that complex input mode is available only in CMOS input

mode.

<24>: Port A Complex Data Active Bit. When this bit is set, the

data input on Ports A and B is interpreted as complex input

(Port A for the in-phase signal and Port B for the quadrature

phase signal). This complex input is passed on as input from

ADC Port A. When this bit is cleared, the data on ADC Port A

and ADC Port B is interpreted as real and independent input.

Note that complex input mode is available only in CMOS input

mode.

<23>: Channel 5 Complex Data Input Bit. When this bit is set,

Channel 5 gets complex input data from the source that is

selected by the crossbar mux select bits. When this bit is cleared,

Channel 5 receives real input data. (See Table 31.)

<22:20>: Channel 5 Crossbar Mux Select Bits. These bits select

the source of input data for Channel 5. (See Table 31.)

Table 31. Channel 5 Input Configuration

Complex Data

Input Bit

Crossbar Mux

Select Bits

Configuration

000

ADC Port A drives input

(real).

001

ADC Port B drives input

(real).

010

ADC Port C drives input

(real).

011

ADC Port D drives input

(real).

100

PN sequence drives input

(real).

000

Ports A and B drive

complex input.

001

Ports C and D drive

complex input.

010

PN sequence drives

complex input.

<19>: Channel 4 Complex Data Input Bit. Similar to Bit <23>

for Channel 4.

<18:16>: Channel 4 Crossbar Mux Select Bits. Similar to Bits

<22:20> for Channel 4.

<15>: Channel 3 Complex Data Input Bit. Similar to Bit <23>

for Channel 3.

<14:12>: Channel 3 Crossbar Mux Select Bits. Similar to Bits

<22:20> for Channel 3.

<11>: Channel 2 Complex Data Input Bit. Similar to Bit <23>

for Channel 2.

<10:8>: Channel 2 Crossbar Mux Select Bits. Similar to Bits

<22:20> for Channel 2.

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