DSP56166ROM datasheet(25/63 Pages) MOTOROLA

25 / 63 page

PRELIMINARY - 6/15/93

DSP56166 Technical Data Sheet

MOTOROLA

AC Electrical Characteristics

— Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)

(Vdd = 5.0 Vdc +/- 10%, TJ = -40 to +125

°C, CL = 50 pF + 1 TTL Load).

Notes:

1. Circuit stabilization delay is required during reset when using an external clock in two cases:

1) after power-on reset, and

2) when recovering from Stop mode.

Num

Characteristics

60MHz

Unit

Min

Max

Delay from General-Purpose Out-

put Valid Caused by the Execution

of the First Interrupt Instruction to

IRQA, IRQB, IRQC Deassertion for

Level Sensitive Fast Interrupts — If

2nd Interrupt Instruction is:

Single Cycle

(see note 2)

Two Cycles

—

cyc-

3cyc-

Synchronous setup time from

IRQA, IRQB, IRQC assertion to

Synchronous falling edge of CLKO

(see note 5, 6)

Falling Edge of CLKO to First Inter-

rupt Vector Address Out Valid after

Synchronous recovery from Wait

State (see Note 3, 5)

27T+

IRQA Width Assertion to Recover

from STOP State(see note 4)

3.6

—

Delay from IRQA Assertion to Fetch

of first instruction (exiting STOP)

OMR bit 6 = 0

(see note1,3)

OMR bit 6 = 1

524303T

47T+3

—

Duration for Level Sensitive IRQA

Assertion to Cause the Fetch of

First IRQA Interrupt Instruction

(exiting STOP)

(see note1,3)

OMR bit 6 = 0

OMR bit 6 = 1

524303T

47T

—

Delay from Level Sensitive IRQA

Assertion to First Interrupt Vector

Address Out Valid (exiting STOP)

(see note1, 3)

OMR bit 6 = 0

OMR bit 6 = 1

524303T

47T+3

—

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