DSP56166ROM datasheet(9/63 Pages) MOTOROLA

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DSP56166

MOTOROLA

PRELIMINARY

ON-CHIP EMULATION (4 PINS)

DSI/OS0

(Debug Serial Input/Chip Status 0) — The

DSI/OS0 pin, when an input, is the pin through which serial

data or commands are provided to the OnCE controller.

The data received on the DSI pin will be recognized only

when the DSP has entered the debug mode of operation.

Data must have valid TTL logic levels before the serial clock

falling edge. Data is always shifted into the OnCE serial port

most significant bit (MSB) first. When the DSP is not in the

debug mode, the DSI/OS0 pin is an output and it provides

information about the chip status. It is used in conjunction

with the OS1 pin.

DSCK/OS1

(Debug Serial Clock/Chip Status 1) — The

DSCK/OS1 pin, when an input, is the pin through which the

serial clock is supplied to the OnCE. The serial clock

provides pulses required to shift data into and out of the

OnCE serial port. Data is clocked into the OnCE on the

falling edge and is clocked out of the OnCE serial port on

the rising edge. When the DSP is not in the debug mode,

the DSCK/OS1pin is an output and it provides information

about the chip status. It is used in conjunction with the OS0

pin.

DSO

(Debug Serial Output) — The debug serial output

provides the data contained in one of the OnCE controller

registers as specified by the last command received from

the command controller. When idle, this pin is high. When

the requested data is available, the DSO line will be

asserted (negative true logic) for nine T cycles (more than

two instruction cycles) to indicate that the serial shift

data. When the chip enters the debug mode due to an

external debug request (DR), an internal software debug

request (DEBUG), a hardware breakpoint occurrence or a

trace/step occurrence, this line will be asserted for eight T

cycles to indicate that the chip has entered the debug mode

and is waiting for commands. Data is always shifted out the

OnCE serial port most significant bit (MSB) first.

(Debug Request Input) — The debug request input

provides a means of entering the debug mode of operation.

This pin when asserted (negative true logic) will cause the

DSP to finish the current instruction being executed, enter

the debug mode, and wait for commands to be entered

from the debug serial input line.

ON-CHIP CODEC (7 PINS)

AUX

(Auxiliary input) — This pin is selected as the analog

input to the A/D converter when the INS bit is set in the

codec control register COCR. This pin should be left

floating when the codec is not used.

BIAS

(Bias current pin) — This input is used to determine

the bias current for the analog circuitry. Connecting a

resistor between BIAS and VGNDA will program the current

bias generator. This pin should be left floating when the

codec is not used.

MIC

(Microphone input) — This pin is selected as the

analog input to the A/D converter when the INS bit is

cleared in the codec control register COCR. This pin should

be left floating when the codec is not used.

SPKP

(Speaker Positive Output) — This pin is the positive

analog output from the on-chip D/A converter. This pin

should be left floating when the codec is not used.

SPKM

(Speaker Negative Output) — This pin is the negative

analog output from the on-chip D/A converter. This pin

should be left floating when the codec is not used.

VRAD

(Voltage Reference Output for the A/D) — This pin is

the output of the op-amp buffer in the reference voltage

generator for the A/D section. It has a value of (2/5) VDDA.

This voltage is used for analog ground internal to the

block.This pin should always be connected to the Ground

through two capacitors, even when the codec is not used.

VRDA

(Voltage Reference Output for the D/A) — This pin is

the output of the op-amp buffer in the reference voltage

generator for the D/A section. It has a value of (2/5) VDDA.

This voltage is used for analog ground internal to the

block.This pin should always be connected to the Ground

through two capacitors, even when the codec is not used.

VDIV

(Voltage Division Output) — This pin is the input to the

op-amp buffer in the reference voltage generator. It is

connected to a resistor divider network located within the

codec block which provides a voltage equal to (2/5)VDDA.

This pin should be connected to the ground via a capacitor

when the codec is used and should be left floating when the

codec is not used.

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