DSP56166ROM datasheet(60/63 Pages) MOTOROLA

60 / 63 page

MOTOROLA

TECHNICAL DATA

SEMICONDUCTOR

MOTOROLA

The DSP56166ROM is the second member of Motorola’s DSP56100 family of HCMOS, low power, 16-bit general purpose Digital

Signal Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166ROM has a built-in

Σ∆

codec and phase locked loop (PLL). This MPU-style DSP also contains, memories, peripherals, and provides a cost effective, high

performance solution to many DSP applications. On-Chip Emulation (OnCE

™) circuitry provides convenient and inexpensive debug

facilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly

simplified by using the OnCE. The DSP56166 ROM based part contains a 12K ROM (8K x 16 program ROM and 4K x 16 data ROM).

The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an

instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56166ROM. The MPU-style program-

ming model and instruction set allow straightforward generation of efficient, compact code. The basic architectures and development

tools of the DSP56100, DSP56000, and DSP96000 families are so similar that learning to design and program one greatly reduces

the time needed to learn the others.

Advance Information

16-bit General Purpose

Digital Signal Processor

DSP56166ROM

Ceramic Quad Flat Pack (CQFP)

Available in a 112 pin, small footprint,

surface mount package.

• Up to 30 Million Instructions per Second (MIPS) at 60

MHz.– 33.3 ns Instruction cycle

• Single-cycle 16 x 16-bit parallel Multiply-Accumulate

• 2 x 40-bit accumulators with extension byte

• Fractional and integer arithmetic with support for

multiprecision arithmetic

• Highly parallel instruction set with unique DSP

addressing modes

• Nested hardware DO loops including infinite loops and

DO zero loop

• Two instruction LMS adaptive filter loop

• Fast auto-return interrupts

• Three external interrupt request pins

• Three 16-bit internal data and three 16-bit internal

address buses

• Individual programmable wait states on the external bus

for program, data, and peripheral memory spaces

• Off-chip memory-mapped peripheral space with

programmable access time and separate peripheral

enable pin

• On-chip memory-mapped peripheral registers

• Low Power Wait and Stop modes

• On-Chip Emulation (OnCE

) for unobtrusive, processor

speed independent debugging

• Operating frequency down to DC

• 5V single power supply

• Low power (HCMOS)

• 4K x 16 on-chip data RAM

• 4K x 16 on-chip data ROM

• 256 x 16 on-chip program RAM

• 8K x 16 on-chip program ROM

• One external 16-bit address bus

• One external 16-bit data bus

• On-chip

Σ∆ voice band codec (A/D-D/A)

– Internal voltage reference (2/5 of positive power

supply)

– No off-chip components required

• 25 general purpose I/O pins

• On-chip, programmable PLL

• Byte-wide Host Interface with DMA support

• Two independent reduced synchronous serial

interfaces

• One 16-bit timer

• 112 pin quad flat pack packaging

• XROM can only be accessed during a single read or the

first read of a dual parallel read instruction (see note on

back.

• No bootstrap ROM

• Reset mode 1 vectors to P:$0100

• PROM area P:$2080 — P:$20FF is reserved and

should not be programmed or accessed by the user

DSP56166ROM Feature List

DSP56166ROM On-chip Resources

Operational Differences Of The ROM Based Part From The RAM Based Part

DSP56100 Family Features

This document contains information on a new product. Speciﬁcations and information herein are subject to change without notice.

Order this document

by DSP56166ROM/D

July 14, 1993

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