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DSP56166ROM датащи(PDF) 46 Page - Motorola, Inc

номер детали DSP56166ROM
подробное описание детали  16-bit General Purpose Digital Signal Processor
PDF  63 Pages
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производитель  MOTOROLA [Motorola, Inc]
домашняя страница  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

DSP56166ROM датащи(HTML) 46 Page - Motorola, Inc

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PRELIMINARY - 6/15/93
MOTOROLA
DSP56166 Technical Data Sheet
36
NOTES:
1. “Host synchronization delay (tHSDL)” is the time period required for the DSP56166 to
sample any external asynchronous input signal, determine whether it is high or low, and
synchronize it to the internal clock.
2. See HOST PORT USAGE CONSIDERATIONS.
3. HREQ is pulled up by 1k
Ω.
4. Only if two consecutive reads from one of these registers are executed.
Num
Characteristic
60MHz
Unit
Min
Max
110
HR/W Low Setup Time Before HEN Asser-
tion
4—
ns
111
HR/W Low Hold Time After HEN Deasser-
tion
4—
ns
112
HR/W High Setup Time to HEN Assertion
4
—
ns
113
HR/W High Hold Time After HEN/HACK
Deassertion
3—
ns
114
HA0-HA2 Setup Time Before HEN Asser-
tion
0—
ns
115
HA0-HA2 Hold Time After HEN Deassertion
6
—
ns
116
DMA HACK Assertion to HREQ Deasser-
tion(see Note 3)
4
2T+
35
ns
117
DMA HACK Deassertion to HREQ
Assertion(see Note 3)
for DMA RXL Read
for DMA TXL Write
for All Other Cases
tHSDL
+3T+4
tHSDL
+2T+4
4
—
—
—
ns
ns
ns
118
Delay from HEN Deassertion to HREQ
Assertion for RXL Read (see Note 3)
tHSDL
+3T+4
—ns
119
Delay from HEN Deassertion to HREQ
Assertion for TXL Write (see Note 3)
tHSDL
+2T+4
—ns
120
Delay from HEN Assertion to HREQ Deas-
sertion for RXL Read, TXL Write
( see Note 3)
13.7
2T+
16.4
ns
AC Electrical Characteristics — Host I/O Timing (Continued)



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