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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56166ROM датащи(PDF) 50 Page - Motorola, Inc |
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DSP56166ROM датащи(HTML) 50 Page - Motorola, Inc |
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50 / 63 page  PRELIMINARY - 6/15/93 MOTOROLA DSP56166 Technical Data Sheet 40 AC Electrical Characteristics — RSSI Timing (VCC = 5.0 Vdc +/- 10%, TJ = -40 ° to + 125° C, CL = 50 pF + 1 TTL Load, see RSSI Figure 1 and 2) T = Icyc / 4 SCK Pin = Serial Clock SFS Pin = Transmit/Receive Frame Sync i ck = Internal Clock and Frame Sync x ck = External Clock and Frame Sync bl = bit length wl = word length NOTE: All the timings for the RSSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a non- inverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK and/or the frame sync SFS in the tables and in the figures. Num Characteristic 60MHz Case Unit Min Max 130 SCK Clock Cycle (see Note 1) TBD — i ck ns 131 SCK Clock High Period TBD — i ck ns 132 SCK Clock Low Period TBD — i ck ns 133 SCK Clock Rise/Fall Time — TBD i ck ns 134 SCK Rising Edge to SFS In (bl) High — TBD i ck ns 135 SCK Rising Edge to SFS In (bl) Low — TBD i ck ns 136 SCK Rising Edge to SFS In (wl) High — TBD i ck ns 137 SCK Rising Edge to SFS In (wl) Low — TBD i ck ns 138 Data In Setup Time Before SCK Falling Edge TBD — i ck ns 139 Data In Hold Time After SCK Falling Edge TBD — i ck ns |
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