MOTOROLA

DSP56166ROM Block Diagram

Note: Since the on-chip XROM is only connected to the XAB1 address bus (see the block diagram above), the data located in this

ROM is only accessible by the first read of a single read instruction or the first read of a dual parallel read instruction.

Therefore, during development using the RAM based part, the data to be mapped in the on-chip XROM on the ROM based

part should not be accessed with a second read during a dual parallel read instruction.

XDB

PDB

GDB

4

7+10

ADDRESS

PROGRAM CONTROL UNIT

MODA/IRQA

MODB/IRQB

ON-CHIP

PERIPHERALS

HOST, RSSI0,

RSSI1, TIMER

GPI/O, CODEC

INTERNAL DATA

BUS SWITCH

AND BIT

MANIPULATION

UNIT

EXTERNAL

ADDRESS

BUS

SWITCH

BUS

CONTROL

EXTERNAL

DATA BUS

SWITCH

PRAM

256 x 16

PROGRAM

ADDRESS

GENERATOR

PROGRAM

DECODE

CONTROLLER

PROGRAM

INTERRUPT

CONTROLLER

DATA ALU

16x16+40 - 40-BIT MAC

TWO 40-BIT ACCUMULATORS

CLOCK

AND PLL

EXTAL

PORT B

OR

HOST

15

CODEC,

PORT C

AND/OR

RSSI0,

RSSI1,

TIMER

RESET

16 BITS

DATA

10

OnCE

SXFC

CLKO

XAB1

XAB2

PAB

ADDRESS

GENERATION

UNIT

16

16

MODC/IRQC

PROM

8K x 16

DATA

RAM

4Kx16

DATA

ROM

4Kx16

PROGRAM

DATA MEMORY

MEMORY

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For availability and literature call your local Motorola Sales Office or Authorized Distributor.

For free application software and information call the Dr. BuB electronic bulletin board:

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(512) 891-3771

(8 data bits, no parity, 1 stop)

In Europe, Japan and Asia Pacific

Contact your regional sales office or Motorola distributor.

Literature Distribution Centers:

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EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.

JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.

ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbor Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.,

Hong Kong.

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