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DSP56166ROM датащи(PDF) 45 Page - Motorola, Inc |
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DSP56166ROM датащи(HTML) 45 Page - Motorola, Inc |
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45 / 63 page ![]() PRELIMINARY - 6/15/93 35 DSP56166 Technical Data Sheet MOTOROLA AC Electrical Characteristics — Host I/O Timing (VCC = 5.0 Vdc +/- 10%, TJ = -40 ° to +125° C, CL = 50 pF + 1 TTL Load, see Host Figures 1 through 6) T = Icyc / 4 cyc=Clock cycle =1/2 instruction cycle= 2 T cycle tHSDL = Host Synchronization Delay Time tsuh : Host processor data setup time Active low lines should be “pulled up” in a manner consistent with the AC and DC specifications Num Characteristic 60MHz Unit Min Max 100 Host Synchronous Delay (see Note 1) T3T ns 101 HEN/HACK Assertion Width a.CVR,ICR, ISR Read (see Note 2,4) b.Read c.Write 2T+ 30 16+tsuh 8.0 — — — ns 102 HEN/HACK Deassertion Width (see Note 2) 27 — ns 103 Minimum Cycle Time Between Two HEN Assertion for Consecu- tive CVR, ICR, ISR reads 4T+ 30 —ns 104 Host Data Input Setup Time Before HEN/HACK Deassertion 3— ns 105 Host Data Input Hold Time After HEN/HACK Deassertion 9— ns 106 HEN/HACK Assertion to Output Data Active from High Impedance 0— ns 107 HEN/HACK Assertion to Output Data Valid —24 ns 108 HEN/HACK Deassertion to Output Data High Impedance —17 ns 109 Output Data Hold Time After HEN/ HACK Deassertion 5— ns |
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