# VSC7212 Gigabit Interconnect Chip

## Features
· ANSI X3T11 Fibre Channel & IEEE 802.3z Gigabit Ethernet compliant
· Up to 2.18Gb/s duplex data rate (1088Mb/s or 784Mb/s configurable)
· 8B/10B encoder/decoder (bypass option available)
· Elastic buffer for cable deskewing
· Tx/Rx rate matching via IDLE insertion/deletion
· Compatible with VSC7211, VSC7214, and VSC7216
· Received data alignment to REFCLK or recovered clock
· PECL Rx signal detect & cable equalization
· Internal loopback modes
· Clock multiplier generates baud rate clock
· Automatic lock-to-reference
· JTAG boundary scan support
· Built-in self test
· 3.3V supply, 1.0W power consumption
· 100-pin TQFP package

## Clock Generation & Configuration
· Clock synthesizer multiplies REFCLK by 10 or 20 (controlled by DUAL input)
· Requires external 0.1µF capacitor for loop filter (NPO or X7R)
· REFCLK can be single-ended TTL or differential PECL

## Transmitter
· 8-bit parallel input (T(7:0)), control inputs (C/D, WSEN)
· TMODE(2:0) controls input timing reference (REFCLK or TBC)
· 8B/10B encoding or bypass mode with 10-bit input
· Serial output via PTX/RTX (PECL, configurable)
· Word Sync Sequence generation via WSEN input

## Receiver
· Serial input via PRX/RRX (PECL, selectable)
· Signal detect outputs (PSDET, RSDET)
· Clock and Data Recovery (CDR) unit
· 8B/10B decoding
· Elastic buffer for timing adjustments
· RMODE(1:0) selects output timing reference (REFCLK or recovered clock)
· Outputs: R(7:0) data, ERR, KCH, IDLE

## Operation Modes
· Encoder Bypass: Bypasses 8B/10B encoding.
· Word Sync Generation: Used to align receiver channels.
· Multiple VSC7212/VSC7214/VSC7216 parallel operation supported with proper configuration.

## Compatibility
· Compatible with VSC7211 and VSC7214 at serial link level.
· Differences are in the resync state and some parallel interface configurations.
· VSC7212 KCHAR input is static and does not have the same input timing as VSC7211/VSC7214.