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HT45F2020 датащи(PDF) 34 Page - Holtek Semiconductor Inc |
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HT45F2020 датащи(HTML) 34 Page - Holtek Semiconductor Inc |
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34 / 85 page ![]() Rev. 1.00 34 April 11, 2017 Rev. 1.00 35 April 11, 2017 HT45F2020/HT45F2022 Sound Effect Generator Flash MCU HT45F2020/HT45F2022 Sound Effect Generator Flash MCU Watchdog Timer Operation TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverflows.Thismeans thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe WatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisis doneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumps toanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthe correctmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Withregardto theWatchdogTimerenable/disablefunction,therearefivebits,WE4~WE0,intheWDTCregister toofferadditionalenable/disableandresetcontroloftheWatchdogTimer.TheWDTfunction willbedisabledwhentheWE4~WE0bitsaresettoavalueof10101B.TheWDTfunctionwillbe enablediftheWE4~WE0bitsvalueisequalto01010B.IftheWE4~WE0bitsaresettoanyother valuesbytheenvironmentalnoiseorsoftwaresetting,except01010Band10101B,itwillresetthe deviceafteradelaytime,tSRESET.Afterpoweronthesebitswillhavethevalueof01010B. WE4~WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandset thestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer time-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStack Pointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer. ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101Bwrittenintothe WE4~WE0bitfiled,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethird isviaaHALTinstruction. ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse thesingle“CLRWDT”instructiontocleartheWDT. Themaximumtimeoutperiodiswhenthe215divisionratioisselected.Asanexample,witha 32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround1 secondsforthe215divisionratio,andaminimumtimeoutof8msforthe28divisionration. “ CLR WDT”Instruction 8-stage Divider WDT Prescaler WE4~WE0 bits WDTC Register Reset MCU LIRC fLIRC fLIRC/28 8-to- 1 MUX CLR WS2~WS0 WDT Time-out (28/fLIRC ~215/fLIRC) “ HALT”Instruction Watchdog Timer |
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