STM32F410RB datasheet(17/142 Pages) STMICROELECTRONICS

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STM32F410x8/B

Functional overview

3.4

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5

Embedded Flash memory

The devices embed up to 128 Kbytes of Flash memory available for storing programs and

data, plus 512 bytes of OTP memory organized in 16 blocks which can be independently

locked.

To optimize the power consumption the Flash memory can also be switched off in Run or in

Sleep mode (see Section 3.18: Low-power modes).

Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between

power saving and startup time.

Before disabling the Flash, the code must be executed from the internal RAM.

3.6

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a software

signature during runtime, to be compared with a reference signature generated at link-time

and stored at a given memory location.

3.7

Embedded SRAM

All devices embed 32 Kbytes of system SRAM which can be accessed (read/write) at CPU

clock speed with 0 wait states

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