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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F410RB датащи(PDF) 85 Page - STMicroelectronics |
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STM32F410RB датащи(HTML) 85 Page - STMicroelectronics |
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85 / 142 page  DocID028094 Rev 5 85/142 STM32F410x8/B Electrical characteristics 118 tLOCK PLL lock time VCO freq = 100 MHz 75 - 200 µs VCO freq = 432 MHz 100 - 300 Jitter(3) Cycle-to-cycle jitter System clock 100 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design. 3. The use of two PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization. Table 44. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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