ST72561J4-Auto datasheet(137/324 Pages) STMICROELECTRONICS

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ST72561-Auto

8-bit timer (TIM8)

Doc ID 12370 Rev 8

137/324

Load the OC2R register with the value corresponding to the period of the signal using

the formula in the opposite column.

Load the OC1R register with the value corresponding to the period of the pulse if

(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.

Select the following in the CR1 register:

–

Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with the OC1R register.

–

Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with the OC2R register.

Select the following in the CR2 register:

–

Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.

–

Set the PWM bit.

–

Select the timer clock (CC[1:0]) (see Table 55).

If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the

OC2R and OC1R registers.

If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.

The OCiR register value required for a specific timing application can be calculated using

the following formula:

Where:

Signal or pulse period (in seconds)

fCPU

PLL output x2 clock frequency in hertz (or fOSC/2 if PLL is not enabled)

PRESC =

Timer prescaler factor (2, 4, 8 or 8000 depending on CC[1:0] bits, see

Table 55)

The Output Compare 2 event causes the counter to be initialized to FCh (see Figure 69)

Note:

The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be

Counter

OCMP1 = OLVL2

Counter

= OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FCh

ICF1 bit is set

OCiR Value =

t * fCPU

PRESC

- 5

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