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ST72561J4-Auto датащи(PDF) 70 Page - STMicroelectronics

номер детали ST72561J4-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561J4-Auto датащи(HTML) 70 Page - STMicroelectronics

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Power saving modes
ST72561-Auto
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Doc ID 12370 Rev 8
Figure 30.
AWUF halt timing diagram
Figure 31.
AWUFH mode flow-chart
Note:
1
WDGHALT is an option bit. See option byte section for more details.
2
Peripheral clocked with an external clock source can still be active.
3
Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode
(such as external interrupt). Refer to Table 16 for more details.
4
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
AWUFH interrupt
fCPU
RUN MODE
HALT MODE
256 or 4096 tCPU
RUN MODE
fAWU_RC
Clear
by software
tAWU
RESET
INTERRUPT 3)
Y
N
N
Y
CPU
MAIN OSC
PERIPHERALS 2)
I[1:0] BITS
OFF
OFF
10
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
MAIN OSC
PERIPHERALS
I[1:0] BITS
ON
OFF
XX 4)
ON
CPU
MAIN OSC
PERIPHERALS
I[1:0] BITS
ON
ON
XX 4)
ON
256 OR 4096 CPU CLOCK
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT 1)
0
WATCHDOG
RESET
1
CYCLE
AWU RC OSC
ON
AWU RC OSC
OFF
AWU RC OSC
OFF
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)



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