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ST72561J4-Auto датащи(PDF) 54 Page - STMicroelectronics

номер детали ST72561J4-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72561J4-Auto датащи(HTML) 54 Page - STMicroelectronics

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Interrupts
ST72561-Auto
54/324
Doc ID 12370 Rev 8
Figure 20.
Nested interrupt management
6.5
Interrupt register description
6.5.1
CPU CC register interrupt bits
Read/Write
Reset value: 111x 1010 (xAh)
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt software priority.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 15: Dedicated interrupt instruction set on page 55).
MAIN
IT2
TLI
MAIN
IT0
3
2
1
3
3
3/0
3
11
00
01
11
11
11
RIM
IT1
IT4
IT4
IT1
IT2
IT3
I1
I0
11 / 10
10
SOFTWARE
PRIORITY
LEVEL
7
0
11
I1
H
I0
N
Z
C
Table 13.
Interrupt software priority levels
Interrupt software priority
Level
I1
I0
Level 0 (main)
Low
High
10
Level 1
0
1
Level 2
0
Level 3 (= interrupt disable(1))
1.
TLI, TRAP and RESET events can interrupt a level 3 program.
11



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