ST72561J4-Auto datasheet(90/324 Pages) STMICROELECTRONICS

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Main clock controller with real time clock MCC/RTC

ST72561-Auto

90/324

Doc ID 12370 Rev 8

10.4

Low power modes

10.5

Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is

set and the interrupt mask in the CC register is not active (RIM instruction).

Note:

The MCC/RTC interrupt wakes up the MCU from ACTIVE HALT mode, not from HALT or

AWUF HALT mode.

10.6

10.6.1

MCC control/status register (MCCSR)

Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the corresponding I/O port. It is set and

cleared by software.

0: MCO alternate function disabled (I/O pin free for general-purpose I/O)

1: MCO alternate function enabled (fOSC2 on I/O port)

Bits 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow modes. Their

action is conditioned by the setting of the SMS bit. These two bits are set and cleared by

software

Table 38.

Effect of low power modes on MCC/RTC

Mode

Description

WAIT

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit from WAIT mode.

ACTIVE HALT

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.

MCC/RTC interrupt cause the device to exit from ACTIVE HALT mode.

HALT

and

AWUF HALT

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from

HALT” capability.

Table 39.

MCC/RTC Interrupt control wake-up capability

Interrupt event

Event

flag

Enable

control

bit

Exit

from

wait

Exit

from

halt

Time base overflow event

OIF

OIE

Yes

No1)

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

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