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ST72561J4-Auto датащи(PDF) 87 Page - STMicroelectronics

номер детали ST72561J4-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561J4-Auto датащи(HTML) 87 Page - STMicroelectronics

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ST72561-Auto
Window watchdog (WWDG)
Doc ID 12370 Rev 8
87/324
9.8
Using halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled.
●
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
9.9
Interrupts
None.
9.10
Register description
9.10.1
Control register (WDGCR)
Read/Write
Reset value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2
cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes
cleared).
9.10.2
Window Register (WDGWR)
Read/ write
Reset value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
These bits contain the window value to be compared to the downcounter.
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
7
0
-
W6W5
W4W3
W2
W1
W0



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