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ST72561J4-Auto датащи(PDF) 77 Page - STMicroelectronics

номер детали ST72561J4-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72561J4-Auto датащи(HTML) 77 Page - STMicroelectronics

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ST72561-Auto
I/O ports
Doc ID 12370 Rev 8
77/324
Warning:
The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
8.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 33.
Interrupt I/O port state transitions
8.4
I/O port register configurations
The I/O port register configurations are summarized as follows.
8.4.1
Standard ports
01
floating/pull-up
interrupt
INPUT
00
floating
(reset state)
INPUT
10
open-drain
OUTPUT
11
push-pull
OUTPUT
XX
= DDR, OR
Table 28.
Configuration of PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0
Mode
DDR
OR
Floating input
0
0
Pull-up input
1
Open drain output
1
0
Push-pull output
1



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