ST72561J4-Auto datasheet(141/324 Pages) STMICROELECTRONICS

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ST72561-Auto

8-bit timer (TIM8)

Doc ID 12370 Rev 8

141/324

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the

length of the pulse depends on the value of OC1R register; the period depends on the

value of OC2R register.

Bit 3, 2 = CC[1:0] Clock Control.

The timer clock mode depends on these bits:

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = Reserved, must be kept at 0.

13.7.3

Control/status register (CSR)

Read only (except bit 2 R/W)

Reset value: 0000 0000 (00h)

Bit 7 = ICF1 Input Capture Flag 1.

0: no input capture (reset value).

1: an input capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read or

write the IC1R register.

Bit 6 = OCF1 Output Compare Flag 1.

0: no match (reset value).

1: the content of the free running counter has matched the content of the OC1R

Bit 5 = TOF Timer Overflow Flag.

0: no timer overflow (reset value).

1: the free running counter rolled over from FFh to 00h. To clear this bit, first read the

SR register, then read or write the CTR register.

Table 55.

Clock control bits

Timer clock

CC1

CC0

fCPU / 4

fCPU / 2

fCPU / 8

fOSC2 / 8000

(1)

Not available in Slow mode in ST72F561.

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

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