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ST72561J4-Auto датащи(PDF) 47 Page - STMicroelectronics

номер детали ST72561J4-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72561J4-Auto датащи(HTML) 47 Page - STMicroelectronics

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ST72561-Auto
Supply, reset and clock management
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If trv is greater than 256 or 4096 cycles then:
●
If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then two AVD
interrupts will be received: The first when the AVDIE bit is set and the second when the
threshold is reached.
●
If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached, then only one
AVD interrupt occurs.
Figure 16.
Using the AVD to monitor VDD
5.6.3
Low power modes
5.6.4
Interrupts
The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask
in the CC register is reset (RIM instruction).
VDD
VIT+(AVD)
VIT-(AVD)
AVDF bit
0
0
RESET VALUE
IF AVDIE bit = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS
INTERRUPT PROCESS
VIT+(LVD)
VIT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
1
1
trv VOLTAGE RISE TIME
Table 9.
Effect of low power modes on SI
Mode
Description
WAIT
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
HALT
The SICSR register is frozen.
Table 10.
Interrupt control/wake-up capability
Interrupt event
Event
flag
Enable
control
bit
Exit
from
wait
Exit
from
halt
AVD event
AVDF
AVDIE
Yes
No



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