ST72344K2 datasheet(156/247 Pages) STMICROELECTRONICS

номер детали	ST72344K2

подробное описание детали	SCI asynchronous serial interface

PDF	247 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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156 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

156/247

Doc ID 12321 Rev 6

master mode transmission. The resetting of the BUSY bit can then be handled in a

similar manner as the BERR flag being set.

●

AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by

hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.

The AF bit is cleared by reading the I2CSR2 register. However, if read before the

completion of the transmission, the AF flag will be set again, thus possibly generating a

new interrupt. Software must ensure either that the SCL line is back at 0 before reading

the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse

of a transmitted byte.

●

ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and

the interface goes automatically back to slave mode (the M/SL bit is cleared).

Note:

In all these cases, the SCL line is not held low; however, the SDA line can remain low if the

last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL

line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.

ST72344K2 датащи(PDF) 156 Page - STMicroelectronics