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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72344K2 датащи(PDF) 160 Page - STMicroelectronics |
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ST72344K2 датащи(HTML) 160 Page - STMicroelectronics |
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160 / 247 page  On-chip peripherals ST72344xx, ST2345xx 160/247 Doc ID 12321 Rev 6 Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). ● In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. ● In slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 70 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 69) is detected. I2C status register 1 (SR1) Reset value: 0000 0000 (00h) 7 0 EVF ADD10 TRA BUSY BTF ADSL M/SL SB Read Only |
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