ST72344K2 datasheet(154/247 Pages) STMICROELECTRONICS

154 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

154/247

Doc ID 12321 Rev 6

new interrupt. Software must ensure either that the SCL line is back at 0 before reading

the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse

of a transmitted byte.

Note:

In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits

transmitted are all 0. It is then necessary to release both lines by software. The SCL line is

not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.

How to release the SDA / SCL lines

Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released

after the transfer of the current byte.

SMBus compatibility

ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes,

SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave

Driver For ST7 I2C Peripheral.

Master mode

To switch from default Slave mode to Master mode a Start condition generation is needed.

Start condition

Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start condition.

Once the Start condition is sent:

●

The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register

with the Slave address, holding the SCL line low (see Figure 69 Transfer sequencing

EV5).

Slave address transmission

Then the slave address is sent to the SDA line via the internal shift register.

In 7-bit addressing mode, one address byte is sent.

In 10-bit addressing mode, sending the first byte including the header sequence causes the

following event:

●

The EVF bit is set by hardware with interrupt generation if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register,

holding the SCL line low (see Figure 69 Transfer sequencing EV9).

Then the second address byte is sent by the interface.

After completion of this transfer (and acknowledge from the slave if the ACK bit is set):

●

The EVF bit is set by hardware with interrupt generation if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the CR register

(for example set PE bit), holding the SCL line low (see Figure 69 Transfer sequencing

EV6).

Next the master must enter Receiver or Transmitter mode.

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