ST72344K2 datasheet(47/247 Pages) STMICROELECTRONICS

47 / 247 page

ST72344xx, ST2345xx

Supply, reset and clock management

Doc ID 12321 Rev 6

47/247

Figure 15.

reset sequence phases

7.5.2

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up

resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Section 13: Electrical

characteristics for more details.

A reset signal originating from an external source must have a duration of at least th(RSTL)in

in order to be recognized (see Figure 17). This detection is asynchronous and therefore the

MCU can enter reset state even in Halt mode.

Figure 16.

Reset block diagram

See Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In

a noisy environment, it is recommended to follow the guidelines mentioned in Section 13:

Electrical characteristics.

If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 17),

the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see

long ext. Reset in Figure 17). Starting from the external RESET pulse recognition, the

device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

7.5.3

External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must

ensure by means of an external reset circuit that the reset signal is held low until VDD is over

the minimum level specified for the selected fOSC frequency (see Section 13.3: Operating

conditions).

A proper reset signal for a slow rising VDD supply can generally be provided by an external

RC network connected to the RESET pin.

RESET

Active phase

Internal Reset

256 or 4096 clock cycles

Fetch

vector

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

Filter

ILLEGAL OPCODE RESET (1)

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