ST72344K2 datasheet(58/247 Pages) STMICROELECTRONICS

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Interrupts

ST72344xx, ST2345xx

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Doc ID 12321 Rev 6

8.5.2

Interrupt software priority registers (ISPRX)

Reset value: 1111 1111 (FFh)

These four registers contain the interrupt software priority of each interrupt vector.

●

Each interrupt vector (except reset and TRAP) has corresponding bits in these

registers where its own software priority is stored. This correspondence is shown in the

following table.

●

Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1

and I0 bits in the CC register.

●

Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is

kept. (example: previous = CFh, write = 64h, result = 44h)

The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and

I0 bits of the CC register are both set.

Caution:

If the I1_x and I0_x bits are modified while the interrupt x is executed, the following behavior

has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previous one, the interrupt x is re-entered.

Otherwise, the software priority stays unchanged up to the next interrupt request (after the

IRET of the interrupt x).

ISPR0

I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

I1_0

I0_0

ISPR1

I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

ISPR2

I1_11

I0_11

I1_10

I0_10

I1_9

I0_9

I1_8

I0_8

ISPR3

I1_13

I0_13

I1_12

I0_12

Read/Write (bits 7:4 of ISPR3 are read only)

Table 15.

Interrupt vector addresses

Vector address

ISPRx bits

FFFBh-FFFAh

I1_0 and I0_0 bits*

FFF9h-FFF8h

I1_1 and I0_1 bits

...

FFE1h-FFE0h

I1_13 and I0_13 bits

Table 16.

Dedicated interrupt instruction set

Instruction

New description

Function/example

HALT

Entering Halt mode

IRET

Interrupt routine return

Pop CC, A, X, PC

JRM

Jump if I1:0=11 (level 3)

I1:0=11 ?

JRNM

Jump if I1:0<>11

I1:0<>11 ?

POP CC

Pop CC from the stack

Mem => CC

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