ST72344K2 datasheet(153/247 Pages) STMICROELECTRONICS

153 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

153/247

Address not matched: the interface ignores it and waits for another Start condition.

Address matched: the interface generates in sequence:

●

Acknowledge pulse if the ACK bit is set.

●

EVF and ADSL bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register, holding the SCL line low (see

Figure 69 Transfer sequencing EV1).

Next, in 7-bit mode read the DR register to determine from the least significant bit (Data

Direction Bit) if the slave must enter Receiver or Transmitter mode.

In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It

will enter transmit mode on receiving a repeated Start condition followed by the header

sequence with matching address bits and the least significant bit set (11110xx1).

Slave receiver

Following the address reception and after SR1 register has been read, the slave receives

bytes from the SDA line into the DR register via the internal shift register. After each byte the

interface generates in sequence:

●

Acknowledge pulse if the ACK bit is set

●

EVF and BTF bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register,

holding the SCL line low (see Figure 69 Transfer sequencing EV2).

Slave transmitter

Following the address reception and after SR1 register has been read, the slave sends

bytes from the DR register to the SDA line via the internal shift register.

The slave waits for a read of the SR1 register followed by a write in the DR register, holding

the SCL line low (see Figure 69 Transfer sequencing EV3).

When the acknowledge pulse is received:

●

The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Closing slave communication

After the last data byte is transferred a Stop Condition is generated by the master. The

interface detects this condition and sets:

●

EVF and STOPF bits with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR2 register (see Figure 69 Transfer sequencing

EV4).

Error cases

●

BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the

EVF and the BERR bits are set with an interrupt if the ITE bit is set.

If it is a Stop, then the interface discards the data, released the lines and waits for

another Start condition.

If it is a Start, then the interface discards the data and waits for the next slave address

on the bus.

●

AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with

an interrupt if the ITE bit is set.

The AF bit is cleared by reading the I2CSR2 register. However, if read before the

completion of the transmission, the AF flag will be set again, thus possibly generating a

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