ST72344K2 datasheet(155/247 Pages) STMICROELECTRONICS

155 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

155/247

Note:

In 10-bit addressing mode, to switch the master to Receiver mode, the software must

generate a repeated Start condition and resend the header sequence with the least

significant bit set (11110xx1).

Master receiver

Following the address transmission and after SR1 and CR registers have been accessed,

the master receives bytes from the SDA line into the DR register via the internal shift

●

Acknowledge pulse if the ACK bit is set

●

EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register,

holding the SCL line low (see Figure 69 Transfer sequencing EV7).

To close the communication: before reading the last byte from the DR register, set the STOP

bit to generate the Stop condition. The interface goes automatically back to slave mode

(M/SL bit cleared).

Note:

In order to generate the non-acknowledge pulse after the last received data byte, the ACK

bit must be cleared just before reading the second last data byte.

Master transmitter

Following the address transmission and after SR1 register has been read, the master sends

bytes from the DR register to the SDA line via the internal shift register.

The master waits for a read of the SR1 register followed by a write in the DR register,

holding the SCL line low (see Figure 69 Transfer sequencing EV8).

When the acknowledge bit is received, the interface sets:

●

EVF and BTF bits with an interrupt if the ITE bit is set.

To close the communication: after writing the last byte to the DR register, set the STOP bit to

generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit

cleared).

Error cases

●

BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the

EVF and BERR bits are set by hardware with an interrupt if ITE is set.

Note that BERR will not be set if an error is detected during the first pulse of each 9-bit

transaction:

Single Master Mode

If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will

not be set and transfer will continue however the BUSY flag will be reset. To work

around this, slave devices should issue a NACK when they receive a misplaced Start or

Stop. The reception of a NACK or BUSY by the master in the middle of communication

gives the possibility to re-initiate transmission.

Multimaster Mode

Normally the BERR bit would be set whenever unauthorized transmission takes place

while transfer is already in progress. However, an issue will arise if an external master

generates an unauthorized Start or Stop while the I2C master is on the first pulse of a

9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C

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