ST72344K2 datasheet(143/247 Pages) STMICROELECTRONICS

143 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

143/247

cleared by a software sequence (an access to the SCISR register followed by a read to

the SCIDR register).

0: Data is not received

1: Received data is ready to be read

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when an Idle Line is detected. An interrupt is generated if

the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to

the SCISR register followed by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

Note:

The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line

occurs).

Bit 3 = OR Overrun error.

This bit is set by hardware when the word currently being received in the shift register is

ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated

if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to

the SCISR register followed by a read to the SCIDR register).

0: No Overrun error

1: Overrun error is detected

Note:

When this bit is set, the RDR register content is not lost but the shift register is overwritten.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected on a received frame. It is cleared by

a software sequence (an access to the SCISR register followed by a read to the SCIDR

0: No noise is detected

1: Noise is detected

Note:

This bit does not generate interrupt as it appears at the same time as the RDRF bit which

itself generates an interrupt.

Bit 1 = FE Framing error.

This bit is set by hardware when a desynchronization, excessive noise or a break

character is detected. It is cleared by a software sequence (an access to the SCISR

0: No Framing error is detected

1: Framing error or break character is detected

Note:

This bit does not generate an interrupt as it appears at the same time as the RDRF bit which

itself generates an interrupt. If the word currently being transferred causes both frame error

and overrun error, it is transferred and only the OR bit is set.

Bit 0 = PE Parity error.

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by

a software sequence (a read to the status register followed by an access to the SCIDR

data register). An interrupt is generated if PIE = 1 in the SCICR1 register.

0: No parity error

1: Parity error

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