ST72344K2 datasheet(146/247 Pages) STMICROELECTRONICS

146 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

146/247

Doc ID 12321 Rev 6

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or not. It is set and cleared by software

and can be cleared by hardware when a wake-up sequence is recognized.

0: Receiver in active mode

1: Receiver in mute mode

Note:

Before selecting Mute mode (by setting the RWU bit), the SCI must first receive a data byte;

otherwise, it cannot function in Mute mode with wake-up by Idle line detection.

In Address Mark Detection Wake-Up configuration (WAKE bit = 1), the RWU bit cannot be

modified by software while the RDRF bit is set.

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note:

If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of

the current word.

Data register (SCIDR)

Reset value: Undefined

Contains the Received or Transmitted data character, depending on whether it is read from

or written to.

The Data register performs a double function (read and write) since it is composed of two

registers, one for transmission (TDR) and one for reception (RDR).

The TDR register provides the parallel interface between the internal bus and the output

shift register (see Figure 63).

The RDR register provides the parallel interface between the input shift register and the

internal bus (see Figure 63).

Baud rate register (SCIBRR)

Reset value: 0000 0000 (00h)

Bits 7:6 = SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard clock division ranges as shown in Figure 59.

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

Read/Write

SCP1

SCP0

SCT2

SCT1

SCT0

SCR2

SCR1

SCR0

Read/Write

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