ST72344K2 datasheet(144/247 Pages) STMICROELECTRONICS

144 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

144/247

Doc ID 12321 Rev 6

Control register 1 (SCICR1)

Reset value: x000 0000 (x0h)

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received word when M = 1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmitted word when M = 1.

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the

current byte transfer in order to reduce power consumption.This bit is set and cleared

by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 4 = M Word length.

This bit determines the word length. It is set or cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note:

The M bit must not be modified during a data transfer (both transmission and reception).

Bit 3 = WAKE Wakeup method.

This bit determines the SCI Wake-Up method, it is set or cleared by software.

0: Idle Line

1: Address Mark

Bit 2 = PCE Parity control enable.

This bit selects the hardware parity control (generation and detection). When the parity

control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1;

8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared

by software. Once it is set, PCE is active after the current byte (in reception and in

transmission).

0: Parity control disabled

1: Parity control enabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled

(PCE bit set). It is set and cleared by software. The parity is selected after the current

byte.

0: Even parity

1: Odd parity

SCID

WAKE

PCE

PIE

Read/Write

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