ST72344K2 datasheet(140/247 Pages) STMICROELECTRONICS

140 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

140/247

Doc ID 12321 Rev 6

SCI clock tolerance

During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th

samples is considered as the bit value. For a valid bit detection, all the three samples should

have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and

10th samples are 0, 1 and 1 respectively, then the bit value is “1”, but the Noise Flag bit is

set because the three samples values are not the same.

Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples

have the desired bit value. This means the clock frequency should not vary more than 6/16

(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when

receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed

3.75%.

Note:

The internal sampling clock of the microcontroller samples the pin value on every falling

edge. Therefore, the internal sampling clock and the time the application expects the

sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit

length is 64 µs), then the 8th, 9th and 10th samples will be at 28 µs, 32 µs and 36 µs

respectively (the first sample starting ideally at 0 µs). But if the falling edge of the internal

clock occurs just before the pin value changes, the samples would then be out of sync by

~4 µs. This means the entire bit length must be at least 40 µs (36 µs for the 10th sample

+ 4 µs for synchronization with the internal sampling clock).

Clock deviation causes

The causes which contribute to the total deviation are:

●

DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the

transmitter is transmitting at a different baud rate).

●

DQUANT: Error due to the baud rate quantization of the receiver.

●

DREC: Deviation of the local oscillator of the receiver: This deviation can occur during

the reception of one complete SCI message assuming that the deviation has been

compensated at the beginning of the message.

●

DTCL: Deviation due to the transmission line (generally due to the transceivers)

All the deviations of the system should be added and compared to the SCI clock tolerance:

DTRA + DQUANT + DREC + DTCL < 3.75%

Noise error causes

See also description of noise error in Receiver.

●

Start bit: the noise flag (NF) is set during start bit reception if one of the following

conditions occurs:

–

A valid falling edge is not detected. A falling edge is considered to be valid if the

three consecutive samples before the falling edge occurs are detected as '1' and,

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