ST72344K2 datasheet(139/247 Pages) STMICROELECTRONICS

139 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

139/247

Setting the RWU bit by software puts the SCI in sleep mode:

●

None of the reception status bits can be set.

●

All the receive interrupts are inhibited.

A muted receiver can be woken up in one of the following two ways:

●

by Idle Line detection if the WAKE bit is reset,

●

by Address Mark detection if the WAKE bit is set.

A receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle

Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.

A receiver wakes up by Address Mark detection when it received a “1” as the most

significant bit of a word, thus indicating that the message is an address. The reception of

this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which

allows the receiver to receive this word normally and to use it as an address word.

Parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can

be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length

defined by the M bit, the possible SCI frame formats are as listed in Table 56.

Note:

In case of wakeup by an address mark, the MSB bit of the data is taken into account and not

the parity bit

Even parity: The parity bit is calculated to obtain an even number of “1s” inside the frame

made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).

Odd parity: The parity bit is calculated to obtain an odd number of “1s” inside the frame

made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set, then the MSB bit of the data written in the data

Reception mode: If the PCE bit is set, then the interface checks if the received data byte

has an even number of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if

odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR

Table 56.

Frame formats

M bit

PCE bit

SCI frame(1)

SB: Start Bit, STB: Stop Bit, PB: Parity Bit.

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data PB | STB |

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