L6751 datasheet(45/59 Pages) STMICROELECTRONICS

45 / 59 page

L6751

Efficiency optimization

Doc ID 023992 Rev 1

45/59

Proper HiZ level can be programmed by adding proper external resistor divider across

PWM1 and PWM2. See Section 4.2 for details about HiZ level recognition. See reference

schematic in Figure 1.

9.3

Gate drive control (GDC)

Gate drive control (GDC) is a proprietary function which allows the L6751 to dynamically

control the Power MOSFET driving voltage in order to further optimize the overall system

efficiency. According to the SVI power state commanded and the configuration received

through the PMBus, the device switches this pin (GDC) between the VCC5 or VDRV

(inputs). By connecting the power supply of external drivers directly to this pin, it is then

possible to carefully control the external MOSFET driving voltage.

In fact, high driving voltages are required to obtain good efficiency in high loading

conditions. On the contrary, in lower loading conditions, such high driving voltage penalizes

efficiency because of high losses in Qgs. GDC allows to tune the MOSFET driving voltage

according to the delivered current.

The default configuration considers GDC always switched to VDRV except when entering

power states higher than PS01h (included): in this case, to further increase efficiency,

simply supply the Phase1 and Phase2 driver through the GDC pin. Their driving voltage is

automatically updated as lower power states are commanded through the SVI interface.

Further optimization may be possible by properly setting the automatic GDC threshold

through the dedicated PMBus command and/or pinstrapping. It is then possible to enable

the gate driving voltage switchover even in PS00h. According to the positioning of the

threshold compared with DPM thresholds, it is possible to achieve different performances.

Simulations and/or bench tests may be of help in defining the best performing configuration

achievable with the active and passive components available.

Figure 13 allows the efficiency improvements with DPM/GDC enabled to be compared with

respect to the standard solution.

Note:

Systems supporting S3 power state may have the VDRV supplied by an OR-ing connection

between 5 Vsby and 12 V or different supply voltage for S0. It is recommended to connect

closely, between the VDRV and VCC5 pins, the OR-ing diode connecting VDRV to the 5

Vsby.

Figure 13.

Efficiency performance with and without enhancements (DPM, GDC)

L6751 датащи(PDF) 45 Page - STMicroelectronics