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L6751 датащи(PDF) 25 Page - STMicroelectronics

номер детали L6751
подробное описание детали  Digitally controlled dual PWM for Intel VR12 and AMD SVI
PDF  59 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6751 датащи(HTML) 25 Page - STMicroelectronics

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L6751
Device configuration and pinstrapping tables
Doc ID 023992 Rev 1
25/59
.
18
75
0000b
(VR12)
CCh / 8Ch
ON
ON
15
75
OFF
10
59
C8h / 88h
ON
10
75
OFF
10
100
C4h / 84h
ON
10
150
OFF
10
220
C0h / 80h
ON
10
Open
OFF
1.
Recommended values, divider needs to be connected between VCC5 pin and GND.
2.
In DDR mode, when enabled, droop has 1/4th scaling factor.
3.
SVI address for multi-phase. Single-phase is further offset by 0001b. In AMD mode, SVI address defaults
according to AMD specifications.
4.
PMBus address for multi-phase (read/write). Single-phase is further offset by 02h. When in VR12 CPU
mode, RCOMP = 12.5 k
Ω to GND, select between Cxh (Open) and 8xh (if installed) PMBus address.
Table 9.
ADDR pinstrapping(1) (2) (continued)
Rdown
[k
Ω]
Rup
[k
Ω]
ADDR
ADDR (3)
PMBADDR
(4)
JMode
DROOP
multi-phase
DROOP
single-phase
Table 10.
BOOT / TMAX pinstrapping(1) (2)
Rdown
[k
Ω]
Rup
[k
Ω]
BOOT - Intel address 0000b(3)
Intel address 0010b, 0100b (3)
TMAX [C]
Multi-
phase
Single-
phase
Link rest
JMode
VBOOT
Link rest
10
1.5
1.000 V
0.000 V
VSA
32
μsec
(debug)
ON
1.500 V
32
μsec
(debug)
130
10
2.7
120
22
6.8
110
10
3.6
100
27
11
1.000 V
1.000 V
VSA
32
μsec
(debug)
10
μsec
(functional)
130
12
5.6
120
82
43
110
13
7.5
100



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