L6751 datasheet(38/59 Pages) STMICROELECTRONICS

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Output voltage monitoring and protection

L6751

38/59

Doc ID 023992 Rev 1

Equation 12

where N is the number of phases and DCR the DC resistance of the inductors. RG

should be designed in worst-case conditions.

–

Design the RIMON in order to have the IMON pin voltage to 1.24 V at the IMAX

current specified by the design. It results:

Equation 13

where IMAX is max. current requested by the processor (see Intel docs for details).

–

Design the RILIM in order to have the ILIM pin voltage to 2.5 V at the IOC_TOT

current specified above. It results:

Equation 14

where IOC_TOT is the overcurrent switch-over threshold previously defined.

–

Adjust the defined values according to application bench testing.

–CILIM in parallel to RILIM can be added with proper time constant to prevent false

OC tripping and/or delay.

–CIMON in parallel to RIMON can be added to adjust the averaging interval for the

current reporting and/or adjust the DPM latencies. Additionally, it can be increased

to prevent false total-OC tripping during DVID.

Note:

This is the typical design flow. Custom design and specifications may require different

settings and ratios between the per-phase OC threshold and the total current OC threshold.

Applications with big ripple across inductors may be required to set per-phase OC to values

different than 110%: design flow should be modified accordingly.

Current reporting precision on IMON may be affected by external layout. The internal ADC is

referenced to the device GND pin: in order to perform the highest accuracy in the current

monitor, RIMON must be routed to the GND pin with dedicated net to avoid GND plane drops

affecting the precision of the measurement.

7.2.2

Overcurrent and power states

When the controller receives an SetPS command through the SVI interface, it automatically

changes the number of working phases. In particular, the maximum number of phases

which L6751 may work in >PS00h is limited to 2 phases regardless of the number N

configured in PS00h.

OC level is then scaled as the controller enters >PS00h, as per Table 14.

1.1

OC_TOT

⋅

() DCR

⋅

OCTH

--------------------------------------------------------------

IMON

1.24V

⋅

MAX

DCR

⋅

---------------------------------

ILIM

2.5V

⋅

OC_TOT

DCR

⋅

-----------------------------------------

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