PC97338 datasheet(172/221 Pages) NSC

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5.19.5 ST_FIFO – Status FIFO

The ST_FIFO is used in MIR and FIR Modes.

It is an 8-level FIFO and is intended to support back-

to-back incoming frames in DMA mode, when an

8237-type DMA controller is used. Each ST_FIFO en-

try contains either status information and frame length

for a single frame, or the number of lost frames.

The bottom entry spans three address locations, and

is accessed via the FRMST, RFRL(L)/LSTFRC and

RFRL(H) registers. The ST_FIFO is flushed when

a hardware reset occurs or when the receiver is soft

reset.

Note: The status and length information of received

frames is loaded into the ST_FIFO whenever the

DMA_EN bit in the extended-mode MCR register is

set to 1 and an 8237 type DMA controller is used, re-

gardless of whether the CPU or the DMA controller is

transferring the data from the RX_FIFO to memory.

This implies that, during testing, if full duplex is en-

abled and a DMA channel is servicing the transmitter

while the CPU is servicing the receiver, the CPU must

still read the ST_FIFO. Otherwise, it fills up and in-

coming frames will be rejected.

FRMST – Frame Status Byte at ST_FIFO

Bottom, Read-Only

This register returns the status byte at the bottom of

the ST_FIFO. If the LOSTFR bit is 0, bits 0 to 4 indi-

cate if any error condition occurred during reception of

the corresponding frame. Error conditions will also af-

fect the error flags in the LSR register.

FIGURE 88. Frame Status Byte Register

RFRL(L)/LSTFRC – Received Frame Length

/Lost-Frame-Count at ST_FIFO Bottom,

Read-Only

This register should be read only when the VLD bit in

FRMST is 1. The information returned depends on the

setting of the LOST_FR bit. Upon reset, all bits are set

to 0.

→ TFRCC terminal count effective in DMA

mode.

B6 SFTSL – ST_FIFO Threshold Select.

An interrupt request is generated when the

ST_FIFO level reaches the threshold or when an

ST_FIFO time-out occurs.

Bit Value

Threshold Level

B7 Reserved.

Read/write 0.

B0 OVR2 – Overrun Error 2.

This bit is set to 1 when incoming characters or

entire frames have been discarded due to the

ST_FIFO being full.

B1 OVR1 – Overrun Error 1.

This bit is set to 1 when incoming characters or

entire frames have been discarded due to the

RX_FIFO being full.

B2 BAD_CRC – CRC Error.

Set to 1 when a mismatch between the received

CRC and the receiver-generated CRC is detect-

ed.

B3 PHY_ERR – Physical Layer Error.

Set to 1 when an encoding error or the sequence

BOF-data-BOF is detected in FIR mode, or an

abort condition is detected in MIR mode.

B4 MAX_LEN – Maximum Frame Length Exceed-

ed.

Set to 1 when a frame exceeding the maximum

length has been received.

B5 Reserved.

Returned data is indeterminate.

B6 LOST_FR – Lost Frame Indicator Flag.

Indicates the type of information provided by this

ST_FIFO entry.

→ Entry provides status information and length

for a received frame.

→ Entry provides overrun indications and num-

ber of lost frames.

B7 VLD – ST_FIFO Entry Valid.

When set to 1, the bottom ST_FIFO entry con-

tains valid data.

765

210

Reset

Required

BAD_CRC

MAX_LEN

Reserved

LOST_FR

VLD

OVR2

OVR1

PHY_ERR

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