PC97338 datasheet(170/221 Pages) NSC

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5.18.4 TFRL/TFRCC – Transmitter

Frame-Length/Current-Count

These registers share the same addresses. TFRL is

always accessed during write cycles and is used to

program the frame length, in bytes, for the frames to

be transmitted. The frame length value does not in-

clude any appended CRC bytes. TFRL is accessed

during read cycles if the CTEST bit is set to 1, and re-

turns the previously programmed value. Values from

1 to 2

13 –1 can be used. The zero value is reserved

and must not be used. TFRCC is loaded with the con-

tent of TFRL when transmission of a frame begins,

and decrements after each byte is transmitted. It is

read-only and is accessed during CPU read cycles

when the CTEST bit is 0. It returns the number of cur-

rently remaining bytes of the frame being transmitted.

These registers are 13 bits wide and are split into two

independently accessible parts occupying consecu-

tive address locations. TFRL(L) and TFRCC(L) are lo-

cated at the lower address and access the least

significant 8 bits, whereas TFRL(H) and TFRCC(H)

are located at the higher address and access the

most significant 5 bits. To properly program TFRL, the

CPU must always write the lower value into TFRL(L)

first, and then the upper value into TFRL (H). The up-

per 3 bits of TFRL(H) are reserved and must be writ-

ten with 0's. In order for a read access of TFRCC to

return an accurate value, the CPU should always read

TFRCC(L) first, and then TFRCC(H). After reset, the

content of the TFRL register is 800h.

5.18.5 RFRML/RFRCC – Receiver Frame

Maximum-Length/Current-Count

These registers share the same addresses. RFRML

is always accessed during write cycles and is used to

program the maximum frame length, in bytes, for the

frames to be received. The maximum frame length

value includes the CRC bytes. RFRML is accessed

during read cycles if the CTEST bit is set to 1, and re-

turns the previously programmed value.

Values from 4 to 2

13 –1 can be used. The values from

0 to 3 are reserved and must not be used. RFRCC

holds the current byte count of the incoming frame,

and increments after each byte is received. It is read-

only and is accessed during CPU read cycles when

the CTEST bit is 0. These registers are 13 bits wide

and are split into two independently accessible parts

occupying consecutive address locations. RFRML(L)

and RFRCC(L) are located at the lower address and

access

the

least

significant

bits,

whereas

RFRML(H) and RFRCC(H) are located at the higher

address and access the most significant 5 bits. To

properly program RFRML, the CPU must always write

the lower value into RFRML(L) first, and then the up-

per value into RFRML(H). The upper 3 bits of

RFRML(H) are reserved and must be written with 0's.

In order for a read access of RFRCC to return an ac-

curate value, the CPU should always read RFRCC(L)

first, and then RFRCC(H). After reset, the content of

the RFRML register is 800h.

Note: TFRCC and RFRCC are intended for testing

purposes only. Use of these registers for any other

purpose is not recommended.

5.19 BANK 5

TABLE 87. Bank 5 Register

5.19.1 P_BGD – Pipelined Baud

Generator Divisor Register

This register holds the value that determines the new

baud rate following a pipeline operation. It is a 16-bit

wide register and is split into two 8-bit parts,

P_BGD(L) and P_BGD(H), occupying consecutive

address locations. The value written into these regis-

ters will be loaded into the least and most significant

parts of the baud generator divisor register when the

transmitter becomes empty and both the MD_PEN

and BR_PEN bits in the P_MDR register are set to 1.

Upon reset, the content of this register is indetermi-

nate.

5.19.2 P_MDR – Pipelined Mode Register

This register can be read or written in any mode. How-

ever, a pipeline operation will only take place if the

presently selected mode and the target mode are

both IrDA modes.

Furthermore, SIR must be selected in extended mode

and the TX_FIFO1 must be enabled.

Address

Offset

Name

Description

00h

P_BGD(L)

Pipelined Baud Generator

Divisor Set Register

01h

P_BGD(H)

Pipelined Baud Generator

Divisor Set Register

02h

P_MDR

Pipeline Mode Register

03h

LCR/

BSR

Link Control/

Bank Select Registers

04h

IRCR2

Infrared Control Register 2

05h

FRM_ST

Frame Status

06h

RFRL(L)/

LSTFRC

Received Frame Length

(Low Byte)/Lost Frame Count

07h

RFRL(H)

Received Frame Length

(High Byte)

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