PC97338 datasheet(59/221 Pages) NSC

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Bit 4 - SCC1 Bank Select Enable

Enables bank switching. Upon reset, this bit is ini-

tialized to 0.

0 - All attempts to access the extended registers

of SCC1 are ignored. (Default)

1 - SCC1 extended registers accessible.

Bits 5 - SCC2 Normal Power Mode

Upon reset, this bit is initialized to 1.

0 - Low power mode. SCC2’s clock is disabled.

IRSL2, 1 and 0 output signals are set to 0.

The RI2 input signal can be set to generate an

interrupt. Registers are maintained.

1 - Normal power mode - SCC2’s clock is en-

abled. SCC2 is functional, when bit 2 of the

FER register is set to 1.

Bit 6 - SCC2 is Busy

Read only. This bit can be used by power manage-

ment software to decide when to power down

SCC2.

This bit is initialized to 0.

0 - No transfer is in progress. (Default)

1 - A transfer is in progress.

FIGURE 23. Busy Flag Timing

Bit 7 - SCC2 Bank Select Enable

Enables bank switching. Upon reset, this bit is ini-

tialized to 0.

0 - All attempts to access the extended registers

of SCC2 are ignored. (Default)

1 - SCC2 extended registers accessible.

2.3.22 Plug and Play Configuration 2

This register allows configurable mapping of the

FDC’s interrupt and DMA signals onto the ISA inter-

rupts and DMA channels. It allows also configurable

mapping of the parallel port’s DMA signals onto the

ISA DMA channels. Upon reset, PNP2 is initialized to

00110000.

FIGURE 24. PNP2 Register Bitmap

Bits 3-0 - FDC Interrupt Mapping

FDC interrupt mapping in Plug and Play mode.

Upon reset these bits are initialized to 0000.

When enabled it can be routed onto one of the fol-

lowing ISA interrupts: IRQ3-IRQ7, IRQ9-IRQ12

and IRQ15. See Table 23.

Disable means FDC’s interrupt is not routed to any

ISA interrupt. Unpredictable results when invalid

values are written. IRQ5, IRQ12 and IRQ15 can

not always be configured. For more details, refer

to Section 6 on page 190.

It is the software‘s responsibility to route all inter-

rupt sources onto the ISA interrupts correctly.

In Legacy mode, these bits are ignored and the in-

terrupt of the FDC is connected to IRQ6.

TABLE 23. FDC Plug and Play Interrupt Mapping

SCF2 Busy

Flag

UART2 AS

Transmitter

I/O WR

UART2 AS

Receiver SIN2

UART and SIR mode: t = one character + 48*(bit time)

TV Remote: t = 75

µs

Busy Flag

one character time =

(bit time) * (word size + start bit + number of stop bits + parity bit)

Bit time = 1/baudrate

MIR, FIR: t = 32

µs

reset after

time t

Bit 3

Bit 2

Bit 1

Bit 0

Interrupt

Disable

Invalid

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

FDC Interrupt Mapping

FDC DMA Plug and Play Support

Reserved

432

Reset

Required

(PNP2)

Plug and Play Configuration

Index 41h

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