PC97338 datasheet(54/221 Pages) NSC

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1 - During reset, if CFG0 = 0, decode four ad-

dress bits (A15-A12) and compare them to

bits 7-4 of CS0HA. Bits 3-0 of CS0HA and bits

7-0 of CS0LA are ignored.

During reset, if CFG0 = 1, it is illegal to set

this bit to 1.

Bit 4 - CS0 Assert Enable (Write)

0 - Do not enable CS0 assertion on write cycles.

1 - Enable CS0 assertion on write cycles.

Bit 5 - CS0 Assert Enable (Read)

0 - Do not enable CS0 assertion on read cy-

cles.

1 - Enable CS0 assertion on read cycles.

Bits 7,6 - Reserved

These bits are reserved.

2.3.13 Chip Select 1 Low Address

This register holds the low address bits of the moni-

tored I/O address. See CS1HA and CS1CF for com-

plementary description. Bit 0 holds A0.

FIGURE 14. CS1LA Register Bitmap

2.3.14 Chip Select 1 Configuration

This register controls the behavior of the CS1 pin.

CS1 is asserted on non-DMA PIO cycles, when RD or

WR is asserted. CS1 can be asserted only on reads

or writes or on all cycles. The register is initialized to

0 during reset.

FIGURE 15. CS1CF Register Bitmap

Bits 2-0 - Reserved

These bits are reserved.

Bit 3 - Number of Decoded Address Bits

0 - If during reset CFG0 = 0, decode 16 address

bits (A15-A0) and compare them to CS1HA

and CS1LA bits.

If during reset CFG0 = 1, decode 11 address

bits (A10-A0) and compare them to bits 2-0 of

CS1HA and bits 7-0 of CS1LA. Bits 7-3 of

CS1HA are ignored.

1 - If during reset CFG[0]=0, decode 14 address

bits (A15-A2) and compare them to bits 7-0 of

CS1HA and bits 7-2 of CS1LA. Bits 1,0 of

CS1LA are ignored.

If during reset CFG0 = 1. decode nine ad-

dress bits (A10-A2) and compare them to bits

2-0 of CS1HA and bits 7-2 of CS1LA. Bits 7-3

of CS1HA and bits 1-0 of CS1LA are ignored.

Bit 4 - CS1 Assert Enable (Write)

0 - Do not enable CS1 assertion on write cycles.

1 - Enable CS1 assertion on write cycles.

Bit 5 - CS1 Assert Enable (Read)

0 - Do not enable CS1 assertion on read cycles.

1 - Enable CS1 assertion on read cycles.

Bits 7,6 - Reserved

These bits are reserved.

543

Reset

Required

(CS1LA)

Chip Select 1

Index 0Ch

Low Address Register

543

Reset

Required

Reserved

(CS1CF)

Chip Select 1

Index 0Dh

Configuration Register

Number of Decoded Address Bits

CS1 Assert Enable (Write)

CS1 Assert Enable (Read)

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