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0 - WGATE is not active. The write circuitry of the

selected FDD is disabled.

1 - WGATE is active. The write circuitry of the se-

lected FDD is enabled. (Default)

Bit 3 - Read Data Status (RDATA)

If read data was sent, this bit indicates whether an

odd or even number of bits was sent.

Every inactive edge transition of the RDATA disk

interface output signal causes this bit to change

state.

0 - Either no read data was sent or an even num-

ber of bits of read data was sent. (Default)

1 - An odd number of bits of read data was sent.

Bit 4 - Write Data (WDATA)

If write data was sent, this bit indicates whether an

odd or even number of bits was sent.

Every inactive edge transition of the WDATA disk

interface output signal causes this bit to change

state.

0 - Either no write data was sent or an even num-

ber of bits of write data was sent. (Default)

1 - An odd number of bits of write data was sent.

Bit 5 - Drive Select 0 Status

This bit reflects the status of drive select bit 0 in the

Digital Output Register (DOR). See Section 3.3.4.

It is cleared after a hardware reset and unaffected

by a software reset.

0 - Either drive 0 or 2 is selected. (Default)

1 - Either drive 1 or 3 is selected.

Bits 7,6 - Reserved

These bits are reserved and are always 1.

3.3.4

Digital Output Register (DOR),

Offset 010

DOR is a read/write register that can be written at any

time. It controls the drive select and motor enable disk

interface output signals, enables the DMA logic and

contains a software reset bit.

The contents of the DOR is set to 00h after a hard-

ware reset, and is unaffected by a software reset.

Table 36 shows how the bits of DOR select a drive

and enable a motor when bit 4 of the Function Enable

states that should not be decoded to enable any drive

or motor.

When bit 4 of the Function Enable Register (FER) is

1, MTR1 presents a pulse that is the inverse of WR.

This pulse is active whenever an I/O write to address

3F2h or 372h occurs. This pulse is delayed for be-

tween 25 and 80 nsec after the leading edge of WR.

The leading edge of this pulse can be used to clock

data into an external latch (e.g., 74LS175).

Address 3F2h is used if the FDC is located at the pri-

mary address (bit 5 of FER is 0) and address 372h is

used if the FDC is located at the secondary address

(bit 5 of FER is 1). See Table 9 on page 46.

TABLE 36. Drive and Motor Pin Encoding When

FER 4 = 1

Usually, the motor enable and drive select output sig-

nals for a particular drive are enabled together. Table

37 shows the DOR hexadecimal values that enable

each of the four drives.

TABLE 37. Drive Enable Hexadecimal Values

Digital Output

Control

Signals

Decoded

Functions

MTR DR

76 5432101010

xxx 1 x x 0 0 - 0 0 0

Activate Drive 0

and Motor 0

xx 1 xxx 0 1 - 0 0 1

Activate Drive 1

and Motor 1

x 1 xxxx 1 0 - 0 1 0

Activate Drive 2

and Motor 2

1 xxxxx 1 1 - 0 1 1

Activate Drive 3

and Motor 3

xxx 0 x x 0 0 - 1 0 0

Activate Drive 0

and Deactivate

Motor 0

xx 0 xxx 0 1 - 1 0 1

Activate Drive 1

and deactivate

Motor 1

x 0 xxxx 1 0 - 1 1 0

Activate Drive 2

and Deactivate

Motor 2

0 xxxxx 1 1 - 1 1 1

Activate Drive 3

and Deactivate

Motor 3

Drive

DOR Hexadecimal Value

01C

12D

24E

38F

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