PC97338 datasheet(60/221 Pages) NSC

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Bits 6-4 - FDC DMA Plug and Play Support

Upon reset these bits are initialized to 011. It is the

software’s responsibility to route all DMA sources

onto the ISA DMA channels correctly. See Table

24.

When a DMA request pin, i.e., DRQ0, DRQ1,

DRQ2 or DRQ3 is not configured as an FDC DMA

request signal or a Parallel Port DMA request sig-

nal, it is in TRI-STATE.

When a DMA acknowledge pin, i.e., DACK0,

DACK1, DACK0 or DACK3 is not configured as an

FDC DMA acknowledge signal or a parallel port

DMA acknowledge signal, it is ignored.

TABLE 24. FDC Plug and Play DMA Settings

Bit 7 - Reserved

This bit is reserved.

2.3.23 Parallel Port Base Address Low

Byte Register (PBAL), Index 42h

This register holds the low address bits of the parallel

port’s base address.

In Legacy mode, this register is ignored and the base

address of the parallel port is determined by bits 1 and

0 of the FAR register.

In Plug and Play mode when EPP is enabled, bit 0

(A2) must be 0.

This register may be modified only when the parallel

port is disabled. Undefined value when out of reset.

It is the software’s responsibility to configure all devic-

es so there will be no conflicts.

FIGURE 25. PBAL Register Bitmap

2.3.24 Parallel Port Base Address High

Byte Register (PBAH), Index 43h

This register holds the high address bits of the parallel

port’s base address.

In Plug and Play mode, when ECP is enabled, bit 2

(A10) must be 0.

In Legacy mode, this register is ignored and the base

address of the Parallel Port is determined by bits 1

and 0 of the FAR register.

This register may be modified only when the parallel

port is disabled. Undefined value when out of reset.

It is the software’s responsibility to configure all devic-

es so there will be no conflicts.

Invalid

IRQ9

IRQ10

IRQ11

IRQ12

Invalid

IRQ15

Bit 5 Bit 4 Bit 3 FDC DMA Plug and Play Setting

Disabled. FDC DMA is not

connected to any ISA DMA

channel, i.e., it is not connected to

any of the chip’s DMA pins.

FDC DMA request and

acknowledge signals are

connected to DRQ0 and DACK0

pins.

FDC DMA request and

acknowledge signals are

connected to DRQ1 and DACK1

pins.

FDC DMA request and

acknowledge signals are

connected to DRQ2 and DACK2

pins.

FDC DMA request and

acknowledge signals are

connected to DRQ3 and DACK3

pins.

Bit 3

Bit 2

Bit 1

Bit 0

Interrupt

101

Reserved

110

Reserved

111

Reserved

Bit 5 Bit 4 Bit 3 FDC DMA Plug and Play Setting

543

Reset

Required

(PBAL)

Parallel Port Base Address

Index 42h

Low Byte Register

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