PC97338 datasheet(169/221 Pages) NSC

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5.18 BANK 4

TABLE 86. Bank 4 Register Set

5.18.1 TMR – Timer Register

This register is used to program the reload value for

the internal down-counter as well as to read the cur-

rent counter value. TMR is 12 bits wide and is split

into two independently accessible parts occupying

consecutive address locations. TMR(L) is located at

the lower address and accesses the least significant

8 bits, whereas TMR(H) is located at the higher ad-

dress and accesses the most significant 4 bits. Val-

ues from 1 to 2

12 –1 can be used. The zero value is

reserved and must not be used. The upper 4 bits of

TMR(H) are reserved and must be written with 0's.

The timer resolution is 125

µs, providing a maximum

time-out interval of approximately 0.5 seconds. To

properly program the timer, the CPU must always

write the lower value into TMR(L) first, and then the

upper value into TMR(H). Writing into TMR(H) causes

the counter to be loaded. A read of TMR returns the

current counter value if the CTEST bit is 0, or the pro-

grammed reload value if CTEST is 1. In order for a

read access to return an accurate value, the CPU

should always read TMR(L) first, and then TMR(H).

This is because a read of TMR(H) returns the content

of an internal latch that is loaded with the 4 most sig-

nificant bits of the current counter value when TMR(L)

is read. After reset, the content of this register is inde-

terminate.

5.18.2 IRCR1 – Infrared Control

Used to control the timer and counters as well as en-

able the Sharp-IR or SIR infrared mode in the non-ex-

tended mode of operation.

Upon reset, all bits are set to 0.

FIGURE 88. Infrared Control Register 1

5.18.3 LCR/BSR – Link Control/Bank

Select Registers

These Registers are the same as in bank 0.

Address

Offset

Name

Description

00h

TMR(L)

Timer Register (Low Byte)

01h

TMR(H)

Timer Register (High Byte)

02h

IRCR1

Infrared Control Register 1

03h

LCR/

BSR

Link Control/

Bank Select Registers

04h

TFRL(L)/

TFRCC(L)

Transmit Frame Length/

Current Count (Low Byte)

05h

TFRL(H)/

TFRCC(H)

Transmit Frame Length/

Current Count (High Byte)

06h

RFRML(L)/

RFRCC(L)

Receive Frame

Maximum Length/

Current Count (Low Byte)

07h

RFRML(H)/

RFRCC(H)

Receive Frame

Maximum Length/

Current Count (High Byte)

TMR_EN – Timer Enable, Extended Mode

Only.

When this bit is 1, the timer is enabled.

When it is 0, the timer is frozen.

CTEST – Counters Test.

When this bit is set to 1, the TMR register re-

load value, as well as the TFRL and RFRML

reads.

B3–2 IR_SL [1–0] – SIR or Sharp-IR Select, Non-

Extended Mode Only.

These bits are used to select the appropriate

infrared mode when the module is in non-ex-

tended mode.

They are ignored when extended mode is se-

lected.

Bits 3-2

Selected Mode

UART

Reserved

Sharp-IR

SIR

B7–4 Reserved.

Write as 0's.

432

Reset

Required

IR_SL0

TMR_EN

CTEST

IR_SL1

Reserved

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