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PC97338 датащи(PDF) 175 Page - National Semiconductor (TI) |
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PC97338 датащи(HTML) 175 Page - National Semiconductor (TI) |
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175 / 221 page ![]() 175 www.national.com TABLE 91. MIR Beginning Flags 5.21 BANK 7 TABLE 92. Bank 7 Register Set 5.21.1 IRRXDC – Infrared Receiver Demodulator Control Register After reset, the content of this register is 29h, select- ing a frequency range from 34.61 kHz to 38.26 kHz for the CEIR mode, and from 480.0 kHz to 533.3 kHz for Sharp-IR mode. The value of this register is ig- nored if receiver demodulation for both Sharp-IR and CEIR mode is disabled. The available frequency ranges for CEIR and Sharp-IR modes are given in Table 93 through Table 95. FIGURE 88. Intrared Receiver Demodulator Control Register ENCODING Beginning Flags 0000 Reserved 0001 1 0010 2 (Default) 0011 3 0100 4 0101 5 0110 6 0111 8 1000 10 1001 12 1010 16 1011 20 1100 24 1101 28 1110 32 1111 Reserved Address Offset Register Name Description 00h IRRXDC Infrared Receiver Demodulator Control 01h IRTXMC Infrared Transmitter Modulator Control 02h RCCFG CEIR Configuration Register 03h LCR/BSR Link Control/ Bank Select Registers 04h IRCFG1 Infrared Interface Configuration Register 1 05h IRCFG2 Infrared Interface Configuration Register 2 06h IRCFG3 Infrared Interface Configuration Register 3 07h IRCFG4 Infrared Interface Configuration Register 4 B4–0 DFR [4–0] – Demodulator Frequency. These bits determine the subcarrier's center frequency for the CEIR mode. B7–5 DBW [2–0] – Demodulator Bandwidth. These bits determine the demodulator band- width within which the subcarrier signal fre- quency has to fall in order for the signal to be accepted. Used for both Sharp-IR and CEIR modes. 7 6 5 432 10 Reset Required 1 0 0 1 0 1 0 0 DFR2 DFR4 DBW0 DBW1 DBW2 DFR0 DFR1 DFR3 |
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