PC97338 datasheet(53/221 Pages) NSC

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1 - Pin 98 (PQFP) or pin 96 (TQFP) is ADRATE0

open drain output. ADRATE0 has the same

value as DRATE0.

Bit 1 - Reserved

This bit is reserved.

Bit 2 - Enhanced TDR Support

0 - TDR read is a function of bit 0 of the FCR

configuration register.

1 - The Chip provides enhanced TDR support.

Bit 3 - PNF Status

This bit reflects the value of the PNF pin. It is a

read only bit; data written to this bit is ignored. It is

undefined when the pin is configured as DRV2 or

DR23.

This bit is undefined when the pin is configured as

DRV2, DR23, SIRQI3 or IRSL2/

ID2.

Bit 4 - Select DENSEL or ADRATE1

Controls the behavior of pin 48 in the PQFP pack-

age or of pin 46 in the TQFP package.

0 - The pin is used for DENSEL.

1 - The pin is used for ADRATE1.

Bit 5 - ECP CNFGA Bit

The value of this pin is reflected on bit 3 of CNFGA

ECP register.

Bit 6 - DENSEL Polarity

This bit controls the polarity of the DENSEL signal.

Upon reset this bit is initialized to 1, thus selecting

active high DENSEL for 500 Kbps, 1 Mbps and

2 Mbps data rates

0 - DENSEL is active low for data transmission

rates of 500 Kbps, 1 Mbps and 2 Mbps data

rates and active high for rates 250 Kbps and

300 Kbps.

1 - DENSEL is active low for data transmission

rates of 250 Kbps, 300 Kbps data rates and

active high for rates of 500 Kbps, 1 Mbps and

2 Mbps. (Default)

Bit 7 - System Operation Mode

The Chip can be configured to either AT or PS/2

mode.

Upon reset this bit is initialized to 1, thus selecting

AT mode.

0 - PS/2 mode.

1 - AT mode. (Default)

2.3.11 Chip Select 0 Low Address

This register holds the low address bits of the moni-

tored I/O address. See CS0HA and CS0CF for com-

plementary description. Bit 0 holds A0

FIGURE 12. CS0LA Register Bitmap

2.3.12 Chip Select 0 Configuration

This register controls the behavior of the CS0 pin.

CS0 is asserted on non-DMA PIO cycles, when RD or

WR is asserted. CS0 can be asserted only on reads,

or on writes or on all cycles. The register is initialized

to 0 during reset.

FIGURE 13. CS0CF Register Bitmap

Bits 2-0 - Reserved

These bits are reserved.

Bit 3 - Number of Decoded Address Bits

0 - During reset, if CFG0 = 0, decode 16 address

bits (A15-A0) and compare them to CS0HA

and CS0LA bits.

During reset, if CFG0 = 1, decode 11 address

bits (A10-A0) and compare them to bits 2-0 of

CS0HA and bits 7-0 of CS0LA. Bits 7-3 of

CS0HA are ignored.

543

(CS0LA)

Reset

Required

Chip Select 0

Index 0Ah

Low Address Register

543

Reset

Required

Reserved

(CS0CF)

Chip Select 0

Index 0Bh

Configuration Register

Number of Decoded Address Bits

CS0 Assert Enable (Write)

CS0 Assert Enable (Read)

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